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| preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this product without notice. publication# 18514 rev: d amendment/ 0 issue date: october 1997 lan ? sc300 highly integrated, low-power, 32-bit microcontroller distinctive characteristics n highly integrated, single-chip cpu and system logic C optimized for embedded pc applications C combines 32 bit, x86 compatible, low-voltage cpu with memory controller, pc/at peripheral controllers, real-time clock, and pll clock gener- ators C 0.7 micron, low-voltage, cmos process, fully static n enhanced am386 ? sxlv cpu core C 25 mhz or 33 mhz operating frequencies C 3.3 v core, 3.3 v or 5 v memory and i/o C low-power, fully static design for long battery life C system management mode (smm) for power management control n integrated power management functions C internal clock generators (using multiple phase- locked loops and one external 32-khz crystal) C supports cpu system management mode (smm) C multiple operating modes: high speed pll, low speed pll, doze, sleep, suspend, and off. fully static design allows stopped clock. C comprehensive control of system and peripheral clocks C five external power management control pins C suspend refresh of dram array C clock switching during isa cycles C low power consumption: 0.12 mw typical suspend mode power C simultaneous multiple-voltage i/o pads operate at either 3.3 v or 5 v. core operates at 3.3 v for minimum power consumption. n integrated memory controller C controls symmetrically addressable dram or asymmetrical 512 kbyte x 8 bit or 1 mbyte x 16 bit dram or sram as main memory C zero wait-state access with 70 ns, page mode drams C supports up to 16 mbyte system memory C supports up to 16 mbyte of application rom/ flash, and 320 kbyte direct rom bios access. also supports shadow ram C fully pc/at compatible n integrated pc/at-compatible peripheral logic C one programmable interval timer (fully 8254 compatible) C two programmable interrupt controllers (8259a compatible) C two dma controllers (8237a compatible) C built-in real-time clock (146818a compatible), with an additional 114 bytes of ram C internal phase-locked loops (pll) generate all clocks from single 32.768 khz crystal input n bus configurations C 16-bit data path C optional bus configurations: internal lcd controller with subset isa 386 local bus mode with subset isa maximum isa bus mode C four programmable chip selects C built-in 8042 chip select n serial port controller (16450 uart compatible) n bidirectional parallel port with epp n integrates two pcmcia version 2.1 slots n integrated cga-compatible lcd controller C fully 6845 compatible C 16 gray levels in text mode; 2 or 4 levels in graphics mode C supports the following lcd panel sizes: 320 x 240 single scan (2 bpp) 640 x 200 single/dual scan (1 bpp) 480 x 320 single scan (1 bpp)
2 lan?sc300 microcontroller data sheet preliminary general description the lansc300 microcontroller is a highly integrated, low-voltage, single-chip implementation of the am386sxlv microprocessor plus most of the addi- tional logic needed for an at-compatible personal com- puter. it is ideal for embedded pc applications, such as point-of-sale equipment, web appliances, industrial controls, and communication equipment. the lansc300 microcontroller from amd is part of the growing lan family of mobile computing products, which leverage existing amd core modules. the lansc300 microcontroller demonstrates the feasibil- ity of constructing highly integrated components built from standard cores and getting these products to mar- ket quickly. the lansc300 microcontroller does this by combining an am386sxlv low-voltage microprocessor core with a memory control unit, a power management unit (pmu), and the bus control and peripheral control logic of a pc/at-compatible computer. for more information about the am386 microprocessors, see the am386 a sx/sxl/sxlv data sheet , order #21020 and the am386 a dx/dxl data sheet , order #21017. for more information about the lansc310 microcon- troller, see the lan tm sc300 microcontroller program- mers reference manual , order #18470. the lansc300 microcontroller includes a memory controller that supports up to 16 mbyte of dram, flash or rom; power management functions; a bus control- ler that supports local or isa bus; a serial port controller that is 16450 uart compatible; a bidirectional epp- compliant parallel port; a 146818a-compatible real-time clock; internal phase-locked loops for clock generation; and standard pc logic chips (8259a, 8237a, and 8254). the lansc300 microcontrollers true static design and low operating voltage enable battery-powered op- eration and lower weight for embedded pc applica- tions. the internal core of the lansc300 microcontroller operates at 3.3 v and the i/o pads allow either 3.3 v or 5 v operation. lowering typical op- erating voltage from 5 v to 3.3 v can dramatically re- duce power consumption. functionally, the lansc300 microcontroller is a 100% dos/windows-compatible, pc/at-compatible com- puter on a chip that is designed to furnish the customer with a high-performance, low-power system solution, providing state-of-the-art power management in a small physical footprint. the lansc300 microcontroller is available in both 25- and 33-mhz versions, in a 208-lead plastic shrink quad flat pack (qfp) (pqr package) and a 208-lead thin quad flat pack (tqfp) (pql package). note: unless specified otherwise, the timings in this data sheet are based on the 33-mhz version of the lansc300 microcontroller. lan?sc300 microcontroller data sheet 3 preliminary customer service the amd customer service network includes u.s. of- fices, international offices, and a customer training cen- ter. expert technical assistance is available from the amd worldwide staff of field application engineers and factory support staff who can answer e86 family hard- ware and software development questions. hotline and world wide web support for answers to technical questions, amd provides a toll-free number for direct access to our corporate ap- plications hotline. also available is the amd world wide web home page and ftp site, which provides the latest e86 family product information. corporate applications hotline (800) 222-9323 toll-free for u.s. and canada 44-(0) 1276-803-299 u.k. and europe hotline world wide web home page and ftp site to access the amd home page, go to http:// www.amd.com. questions, requests, and input concerning amds www pages can be sent via e-mail to webmas- ter@amd.com. to download documents and software, ftp to ftp.amd.com and log on as anonymous using your e-mail address as a password. or via your web browser, go to ftp://ftp.amd.com. documentation and literature free e86 family information such as data books, users manuals, data sheets, application notes, the fusione86 partner solutions catalog, and other litera- ture is available with a simple phone call. internation- ally, contact your local amd sales office for complete e86 family literature. literature ordering (800) 222-9323 toll-free for u.s. and canada (512) 602-5651 direct dial worldwide 4 lan?sc300 microcontroller data sheet preliminary block diagram acin, blx , extsmi, sus/res m u x mcel , mceh , vpp, reg slot b power management control unit bus controller memory controller mapping registers parallel port control serial port (16450) pcmcia interface interrupt controller (2x8259) programmable interval timer (8254) real-time clock (146818a) clock generators am386sxlv dma controller (2x8237a-5) a23Ca13, ads , d/c ,m/io , w/r , bhe , ble , cpuclk, cpurst, cpurdy lrdy , ldev ras , cas , m we pgp3Cpgp0 ppdwe , ppoen afdt , strb , slct , init ack , busy, error , pe, slct dtr , rts , sout cts , dsr , dcd , sin, rin ma11/sa12C ma0/sa23 mcel , mceh , vpp, reg cd , rdy , wp, bvdx } slot a cd , rdy , wp, bvdx wait (common) irqx pmcx pd15Cpd0 pa23Cpa0 control a20gate, rc 8 042cs , sysclk ior , iow , memr , memw , bale mcs1 6, iocs16 , iochrdy, 0ws dackx , tc, aen dreqx d15Cd0 sa12Csa0 dsmd7Cdsmd0 lcd interface lcd controller local bus controller } dsma14Cdsma0 lfx x32out x32in lan?sc300 microcontroller data sheet 5 preliminary ordering information amd standard products are available in several packages and operating ranges. the order numbers (valid combi- nations) are formed by a combination of the elements below. valid combinations elan sc300C25 elansc300C33 kc kc elansc300C25 ki elansc300C33 ki elansc300C25 vc elansc300C33 vc k valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. lansc300 speed option C25 = 25 mhz C33 = 33 mhz temperature range c = commercial (0 c t ambient 70 c) i = industrial (C40 c < t case 85 c) package type k = 208 lead qfp (plastic shrink quad flat pack) (pqr-208) v = 208 lead tqfp (thin quad flat pack) (pql-208) device number/description lansc300 microcontroller highly integrated, low-power, 32-bit microprocessor and system logic C25 c 6 lan?sc300 microcontroller data sheet preliminary table of contents distinctive characteristics ............................................................................................................ 1 general description ..................................................................................................................... 2 customer service ........................................................................................................................ 3 block diagram ............................................................................................................................. 4 ordering information .................................................................................................................... 5 connection diagram .................................................................................................................. 13 lansc300 microcontroller pin designations ............................................................................ 14 pin designations (sorted by pin number) ................................................................................. 15 pin designations (sorted by pin name) .................................................................................... 17 pin state tables ........................................................................................................................ 24 pin characteristics ................................................................................................................ 24 pin descriptions ......................................................................................................................... 34 memory bus interface................................................................................................................ 34 cas1h [srcs3 ], cas1l [srcs2 ], cas0h [srcs1 ], cas0l [srcs0 ] ............................. 34 doscs ................................................................................................................................. 34 ma11Cma0/sa23Csa12....................................................................................................... 34 mwe ..................................................................................................................................... 34 ras1 Cras0 ......................................................................................................................... 34 romcs ................................................................................................................................. 34 system interface ........................................................................................................................ 35 aen [tdi] .............................................................................................................................. 35 d15Cd0 ................................................................................................................................. 35 dack2 [tck] ........................................................................................................................ 35 dbufoe ............................................................................................................................... 35 drq2 [tdo].......................................................................................................................... 35 endirh ................................................................................................................................ 35 endirl ................................................................................................................................. 35 iochrdy.............................................................................................................................. 35 iocs16 [lcddl0]................................................................................................................. 35 ior ........................................................................................................................................ 35 iow ....................................................................................................................................... 36 irq1, irq14 [lcddl2]......................................................................................................... 36 mcs16 [lcddl1] ................................................................................................................. 36 memr ................................................................................................................................... 36 memw .................................................................................................................................. 36 pirq0 (pirq0/irq3), pirq1 (pirq1/irq6) ....................................................................... 36 rstdrv ............................................................................................................................... 36 sa11Csa0............................................................................................................................. 36 sbhe [lcddl3].................................................................................................................... 36 spkr .................................................................................................................................... 36 tc [tms]............................................................................................................................... 37 keyboard interface .................................................................................................................... 37 8042cs [xtdat] .................................................................................................................. 37 a20gate .............................................................................................................................. 37 rc ......................................................................................................................................... 37 sysclk [xtclk] ................................................................................................................. 37 parallel port interface ................................................................................................................ 37 ack ....................................................................................................................................... 37 afdt [x14out].................................................................................................................... 37 busy .................................................................................................................................... 37 error ................................................................................................................................. 37 init [pcmcwe ] .................................................................................................................... 37 preliminary lan?sc300 microcontroller data sheet 7 pe ......................................................................................................................................... 37 ppdwe [ppdcs ].................................................................................................................. 37 ppoen .................................................................................................................................. 37 slct ..................................................................................................................................... 37 slctin [pcmcoe ]............................................................................................................... 38 strb ..................................................................................................................................... 38 serial port interface ................................................................................................................... 38 cts ....................................................................................................................................... 38 dcd ...................................................................................................................................... 38 dsr ....................................................................................................................................... 38 dtr /cfg1 ............................................................................................................................ 38 rin ........................................................................................................................................ 38 rts /cfg0 ............................................................................................................................ 38 sin ........................................................................................................................................ 38 sout .................................................................................................................................... 38 pcmcia interface ...................................................................................................................... 38 bvd1_a (stschg_a ), bvd1_b (stschg_b ) ................................................................... 38 bvd2_a (spkr_a ), bvd2_b (spkr_b ) ............................................................................. 38 ca24 ..................................................................................................................................... 38 ca25 ..................................................................................................................................... 38 cd_a , cd_b ......................................................................................................................... 38 icdir .................................................................................................................................... 39 mceh_a , mceh_b .............................................................................................................. 39 mcel_a , mcel_b ............................................................................................................... 39 pcmcoe .............................................................................................................................. 39 pcmcwe .............................................................................................................................. 39 rdy_a (ireq_a ), rdy_b (ireq_b ) ................................................................................... 39 reg_a , reg_b .................................................................................................................... 39 rst_a, rst_b ..................................................................................................................... 39 vpp_a, vpp_b ..................................................................................................................... 39 wait_ab .............................................................................................................................. 39 wp_a (iois16a ), wp_b (iois16b )...................................................................................... 39 power management interface .................................................................................................... 40 acin...................................................................................................................................... 40 bl4 Cbl1 ............................................................................................................................... 40 extsmi................................................................................................................................. 40 lph ....................................................................................................................................... 40 pgp3Cpgp0 ......................................................................................................................... 40 pmc4Cpmc0 ........................................................................................................................ 40 sus /res .............................................................................................................................. 40 display interface ........................................................................................................................ 40 cp1 ....................................................................................................................................... 41 cp2 ....................................................................................................................................... 41 dsce .................................................................................................................................... 41 dsma14Cdsma0 ................................................................................................................. 41 dsmd7Cdsmd0 ................................................................................................................... 41 dsoe .................................................................................................................................... 41 dswe ................................................................................................................................... 41 frm ...................................................................................................................................... 41 lcdd0 .................................................................................................................................. 41 lcdd1 .................................................................................................................................. 41 lcdd2 .................................................................................................................................. 41 lcdd3 .................................................................................................................................. 41 8 lan?sc300 microcontroller data sheet preliminary [lcddl3Clcddl0]............................................................................................................... 41 lvdd ..................................................................................................................................... 41 lvee ..................................................................................................................................... 41 m ........................................................................................................................................... 42 miscellaneous interface ............................................................................................................. 42 lf1, lf2, lf3, lf4 (analog inputs) ...................................................................................... 42 x1out [baud_out]............................................................................................................ 42 [x14out] .............................................................................................................................. 42 x32in, x32out .................................................................................................................... 42 local bus interface .................................................................................................................... 42 a23Ca12 ............................................................................................................................... 42 ads ....................................................................................................................................... 42 bhe ....................................................................................................................................... 42 ble ....................................................................................................................................... 42 cpuclk................................................................................................................................ 43 cpurdy ............................................................................................................................... 43 cpurst ............................................................................................................................... 43 d/c ........................................................................................................................................ 43 ldev ..................................................................................................................................... 43 lrdy ..................................................................................................................................... 43 m/io ...................................................................................................................................... 43 w/r ....................................................................................................................................... 43 maximum isa bus interface ...................................................................................................... 43 0ws ...................................................................................................................................... 43 bale ..................................................................................................................................... 43 dack7 , dack6 , dack5 , dack3 , dack2 , dack1 , dack0 .............................................. 43 drq7, drq6, drq5, drq3, drq2, drq1, drq0 ............................................................ 43 iochchk .............................................................................................................................. 43 irq15, irq14, irq12Cirq9, irq7Cirq3, irq1 ................................................................. 44 la23Cla17 ........................................................................................................................... 44 lmeg .................................................................................................................................... 44 jtag boundary scan interface ................................................................................................. 44 jtagen ................................................................................................................................ 44 [tck] ..................................................................................................................................... 44 [tdi] ...................................................................................................................................... 44 [tdo]..................................................................................................................................... 44 [tms]..................................................................................................................................... 44 reset and power ....................................................................................................................... 44 agnd.................................................................................................................................... 44 avcc .................................................................................................................................... 44 gnd ...................................................................................................................................... 45 ioreset .............................................................................................................................. 45 resin ................................................................................................................................... 45 vcc....................................................................................................................................... 45 vcc1..................................................................................................................................... 45 vcc5..................................................................................................................................... 45 vmem ................................................................................................................................... 45 vsys..................................................................................................................................... 45 vsys2................................................................................................................................... 45 functional description ............................................................................................................... 45 am386sxlv cpu core ........................................................................................................ 45 memory controller ................................................................................................................. 46 sram .................................................................................................................................... 49 preliminary lan?sc300 microcontroller data sheet 9 pcmcia slots ....................................................................................................................... 50 the pmu modes and clock generators ............................................................................... 50 lansc300 microcontroller power management .................................................................. 53 micro power off mode .......................................................................................................... 55 core peripheral controllers ................................................................................................... 60 additional peripheral controllers ........................................................................................... 60 parallel port anomalies ......................................................................................................... 62 pc/at support features ....................................................................................................... 62 lcd, local bus, or maximum isa bus controller ................................................................. 65 alternate pin functions .............................................................................................................. 68 cpu local bus interface versus internal lcd interface ....................................................... 69 maximum isa interface versus internal lcd interface ......................................................... 70 alternate pin functions selected via firmware ........................................................................ 71 sram interface ..................................................................................................................... 71 dual-scan lcd data bus ..................................................................................................... 71 unidirectional/bidirectional parallel port ............................................................................... 71 x1out [baud_out] clock source ..................................................................................... 72 pc/xt keyboard ................................................................................................................... 72 pcmcia data path control ................................................................................................... 72 14-mhz clock source ........................................................................................................... 72 isa bus descriptions ................................................................................................................. 73 system test and debug ........................................................................................................ 74 jtag instruction opcodes .................................................................................................... 79 absolute maximum ratings ....................................................................................................... 80 operating ranges...................................................................................................................... 80 thermal characteristics ............................................................................................................. 82 typical power numbers ............................................................................................................. 82 derating curves ......................................................................................................................... 84 voltage partitioning .................................................................................................................... 95 crystal specifications ................................................................................................................ 95 loop filters ................................................................................................................................ 97 ac switching characteristics and waveforms .......................................................................... 98 ac switching test waveforms .............................................................................................. 98 ac switching characteristics over commercial and industrial operating ranges ............... 99 physical dimensions ................................................................................................................ 138 pqr 208, trimmed and formed plastic shrink quad flat pack (qfp) ............................. 138 pql 208, trimmed and formed thin quad flat pack (tqfp) ........................................... 139 list of figures figure 1. pll block diagram .................................................................................................. 51 figure 2. clock steering block diagram ................................................................................. 52 figure 3. typical system design with secondary power supply to maintain rtc when primary power supply is off (dram refresh is optional.) .......................... 56 figure 4. lansc300 microcontroller i/o structure ................................................................. 57 figure 5. lansc300 microcontroller unidirectional parallel port data bus implementation......................................................................................... 61 figure 6. the lansc300 cpu bidirectional parallel port and epp implementation ............. 62 figure 7. typical system block diagram (internal lcd controller) ........................................ 64 figure 8. bus option configuration select .............................................................................. 68 figure 9. 3.3-v i/o drive type e rise time............................................................................ 85 figure 10. 3.3-v i/o drive type e fall time ............................................................................. 85 figure 11. 5-v i/o drive type e rise time............................................................................... 86 10 lan?sc300 microcontroller data sheet preliminary figure 12. 5-v i/o drive type e fall time ................................................................................ 86 figure 13. 3.3-v i/o drive type d rise time............................................................................ 87 figure 14. 3.3-v i/o drive type d fall time ............................................................................. 87 figure 15. 5-v i/o drive type d rise time............................................................................... 88 figure 16. 5-v i/o drive type d fall time ................................................................................ 88 figure 17. 3.3-v i/o drive type c rise time............................................................................ 89 figure 18. 3.3-v i/o drive type c fall time ............................................................................. 89 figure 19. 5-v i/o drive type c rise time............................................................................... 90 figure 20. 5-v i/o drive type c fall time ................................................................................ 90 figure 21. 3.3-v i/o drive type b rise time............................................................................ 91 figure 22. 3.3-v i/o drive type b fall time ............................................................................. 91 figure 23. 5-v i/o drive type b rise time............................................................................... 92 figure 24. 5-v i/o drive type b fall time ................................................................................ 92 figure 25. 3.3-v i/o drive type a rise time............................................................................ 93 figure 26. 3.3-v i/o drive type a fall time ............................................................................. 93 figure 27. 5-v i/o drive type a rise time............................................................................... 94 figure 28. 5-v i/o drive type a fall time ................................................................................ 94 figure 29. x32 oscillator circuit................................................................................................ 96 figure 30. loop-filter component ............................................................................................ 97 figure 31. key to switching waveforms ................................................................................... 98 figure 32. power-up sequence timing .................................................................................. 100 figure 33. micro power off mode exit .................................................................................... 100 figure 34. entering micro power off mode (dram refresh disabled) .................................. 101 figure 35. entering micro power off mode (dram refresh enabled) ................................... 101 figure 36. dram timings, page hit ....................................................................................... 103 figure 37. dram timings, refresh cycle .............................................................................. 103 figure 38. dram first cycle and bank/page miss (read cycles)......................................... 105 figure 39. dram first cycle and bank/page miss (write cycles) ......................................... 107 figure 40. local bus interface ................................................................................................ 109 figure 41. display sram timings .......................................................................................... 111 figure 42. lcd interface timings ........................................................................................... 111 figure 43. pcmcia memory read cycle................................................................................ 113 figure 44. pcmcia memory write cycle................................................................................ 115 figure 45. pcmcia i/o read cycle........................................................................................ 117 figure 46. pcmcia i/o write cycle ........................................................................................ 119 figure 47. bios rom read/write 8-bit cycle........................................................................ 121 figure 48. dos rom read/write 8-bit cycle......................................................................... 123 figure 49. dos rom read/write 16-bit cycle....................................................................... 125 figure 50. isa memory read/write 8-bit cycle ...................................................................... 127 figure 51. isa memory read/write 16-bit cycle .................................................................... 129 figure 52. isa memory read/write 0 wait state cycle.......................................................... 131 figure 53. isa i/o 8-bit read/write cycle .............................................................................. 133 figure 54. isa i/o 16-bit read/write cycle ............................................................................ 135 figure 55. epp data register write cycle.............................................................................. 136 figure 56. epp data register read cycle ............................................................................. 137 preliminary lan?sc300 microcontroller data sheet 11 list of tables table 1. i/o pin voltage level................................................................................................. 24 table 2. memory bus interface ............................................................................................... 25 table 3. system interface ....................................................................................................... 26 table 4. keyboard interface .................................................................................................... 28 table 5. parallel port interface................................................................................................ 28 table 6. serial port interface................................................................................................... 29 table 7. power management interface ................................................................................... 29 table 8. pcmcia interface ..................................................................................................... 30 table 9. display interface........................................................................................................ 31 table 10. miscellaneous interface............................................................................................. 33 table 11. power pins ................................................................................................................ 33 table 12. non-multiplexed address signals provided by ma11Cma0...................................... 34 table 13. dram mode selection .............................................................................................. 46 table 14. ma and sa signal pin sharing.................................................................................. 46 table 15. supported dram/sram configuration .................................................................... 47 table 16. dram address translation (page mode) ................................................................. 48 table 17. dram address translation (enhanced page mode)................................................ 49 table 18. sram access pins ................................................................................................... 49 table 19. sram wait state select logic.................................................................................. 50 table 20. high-speed cpu clock frequencies ........................................................................ 53 table 21. pll output ................................................................................................................ 53 table 22. pmu modes............................................................................................................... 54 table 23. internal clock states ................................................................................................. 54 table 24. internal i/o pulldown states...................................................................................... 59 table 25. parallel port epp mode pin definition ...................................................................... 61 table 26. external resistor requirements................................................................................ 65 table 27. bus option select bit logic....................................................................................... 68 table 28. pins shared between cpu local bus and internal lcd interface functions........... 69 table 29. pins shared between maximum isa bus and internal lcd interface functions ..... 70 table 30. sram interface ......................................................................................................... 71 table 31. dual-scan lcd data bus.......................................................................................... 71 table 32. bidirectional parallel port pin description ................................................................. 71 table 33. x1out clock source pin description....................................................................... 72 table 34. xt keyboard pin description .................................................................................... 72 table 35. pcmcia data path control....................................................................................... 72 table 36. 14-mhz clock source ............................................................................................... 72 table 37. internal lcd controller bus mode isa bus functionality ......................................... 73 table 38. local bus mode additional isa bus functionality..................................................... 73 table 39. maximum isa bus mode additional isa bus functionality....................................... 73 table 40. boundary scan (jtag) cellsorder and type ....................................................... 75 table 41. lansc300 microcontroller jtag instruction opcodes ............................................ 79 table 42. dc characteristics over commercial and industrial operating ranges (plastic shrink quad flat pack (qfp), 33 mhz, 3.3 v)............................................. 80 table 43. dc characteristics over commercial and industrial operating ranges (plastic shrink quad flat pack (qfp), 33 mhz, 5 v)................................................ 81 table 44. commercial and industrial operating voltage ranges at 25................................... 81 table 45. thermal resistance (c/watt) y jt and q ja for 208-pin qfp and tqfp packages .. 82 table 46. typical maximum isa mode power consumption .................................................... 82 table 47. typical internal lcd mode power consumption ...................................................... 83 table 48. i/o drive type description (worst case) .................................................................. 84 table 49. recommended oscillator component value limits.................................................. 96 table 50. loop-filter component values.................................................................................. 97 12 lan?sc300 microcontroller data sheet preliminary table 51. power-up sequencing ............................................................................................. 99 table 52. dram memory interface, page hit and refresh cycle ......................................... 102 table 53. dram first cycle read access ............................................................................. 104 table 54. dram bank/page miss read cycles .................................................................... 104 table 55. dram first cycle write access ............................................................................. 106 table 56. dram bank/page miss write cycles ..................................................................... 106 table 57. local bus interface ................................................................................................. 108 table 58. video ram/lcd interface ....................................................................................... 110 table 59. power management control signals ...................................................................... 110 table 60. pcmcia memory read cycle ................................................................................ 112 table 61. pcmcia memory write cycle ................................................................................ 114 table 62. pcmcia i/o read cycle ........................................................................................ 116 table 63. pcmcia i/o write cycle ........................................................................................ 118 table 64. bios rom read/write 8-bit cycle ........................................................................ 120 table 65. dos rom read/write 8-bit cycle ......................................................................... 122 table 66. dos rom and fast dos rom read/write 16-bit cycles .................................... 124 table 67. isa memory read/write 8-bit cycle ...................................................................... 126 table 68. isa memory read/write 16-bit cycle .................................................................... 128 table 69. isa memory read/write 0 wait state cycle .......................................................... 130 table 70. isa i/o 8-bit read/write cycle .............................................................................. 132 table 71. isa i/o 16-bit read/write cycle ............................................................................ 134 table 72. epp data register write cycle .............................................................................. 136 table 73. epp data register read cycle .............................................................................. 137 lan?sc300 microcontroller data sheet 13 preliminary sout rts /cfg0 13 ma8/sa22 ras1 3 ras 0 2 gnd 1 31 d9 dsma4 (a13/dack6 ) 161 agnd 208 lf4 video pll 207 lf3 low speed pll 206 lf2 internal pll 205 lf1 high speed pll 204 avcc 203 x32out 202 irq1 195 pirq0 (pirq0/irq3) 194 pirq1 (pirq1/irq6) 193 iochrdy 192 gnd 191 lph 190 pgp0 pgp1 188 pgp2 187 pgp3 186 pmc3 185 pmc4 184 dswe (pullup/pullup) 183 lvee (irq15/irq5) 182 frm (irq12/irq12) 181 vcc 180 cp2 (pullup/irq10) 179 cp1 (pulldn/irq15) 178 m (irq4/irq4) 173 dsmd7 (ads /0ws ) 172 dsmd5 (m/io /drq3) 170 dsmd4 (w/r /drq7) 169 dsmd3 (bhe /irq9) 168 dsmd2 (ble /irq11) 167 dsmd1 (lrdy /drq6) 166 dsma0 (nc/pullup) 165 dsma1(pullup/irq7) 164 dsma2 (cpurst/reserved) 163 dsma3 (cpuclk/pullup) 162 dsma5 (a14/dack7 ) 160 dsma6 (a15/dack3 ) 159 dsma7 (a16/dack0 ) 158 gnd 157 4 cas1l [srcs2 ] 5 cas1h [srcs3 ] 6 cas0l [srcs0 ] 7 cas0h [srcs1 ] 8 mwe 9 vmem 10 ma10/sa13 11 ma9/sa23 12 gnd 14 ma7/sa21 15 ma6/sa20 16 ma5/sa19 17 ma4/sa18 18 ma3/sa17 19 ma2/sa16 20 gnd 21 ma1/sa15 22 vmem 23 vcc 24 ma0/sa14 25 d15 26 d14 27 d13 28 d12 29 d11 30 d10 32 d8 33 gnd 34 d7 35 vmem 36 d6 37 d5 38 d4 39 d3 40 d2 41 d1 42 d0 43 doscs 44 romcs 45 sysclk[xtclk] 46 dack2 [tck] 47 aen [tdi] 48 vsys 49 tc [tms] 50 endirl 51 endirh 52 gnd 156 gnd 155 dsma8 (a17/la17) 154 dsma9 (a18/la18) 153 dsma10 (a19/la19) 152 dsma11 (a20/la20) 151 dsma12 (a21/la21) 150 dsma13 (a22/la22) 149 dsma14 (a23/la23) 148 dsmd0 (ldev /rsvd) 147 dsoe (cpurdy /lmeg ) 146 dsce (dack1 / dack1 ) 145 lvdd (a12/bale) 144 lcdd0 (dack5 /dack5 ) 143 sbhe [lcddl3] 142 vsys2 141 resin 140 ioreset 139 spkr 138 pmc1 137 pmc0 136 ca25 135 vcc 134 ca24 133 rst_a 132 reg_a 131 vpp_a 130 mceh_a 129 mcel_a 128 vcc5 127 rst_b 126 reg_b 125 vpp_b 124 mceh_b 123 mcel_b 122 icdir 121 gnd 120 bvd1_b 119 bvd2_b 118 wp_b 117 rdy_b 116 cd _b 115 wait_ab 114 bvd1_a 113 bvd2_a 112 wp_a 111 rdy_a 110 cd _a 109 bl4 108 bl3 107 bl2 106 bl1 105 gnd 53 gnd 54 ior 55 iow 56 memr 57 58 59 dbufoe 60 ma11/sa12 61 sa11 62 sa10 63 sa9 64 sa8 65 vsys 66 sa7 67 sa6 68 gnd 69 sa5 70 sa4 71 sa3 72 73 74 sa0 75 8042cs [xtdat] 76 drq2 [tdo] 77 pmc2 78 79 a20gate 80 afdt [x14out] 81 vcc 82 pe 83 strb 84 slctin [pcmcoe] 85 busy 86 error 87 slct 88 ack 89 init [pcmcwe] 90 ppwde [ppdcs ] 91 ppoen 92 dtr /cfg1 93 94 95 vcc5 96 cts 97 dsr 98 dcd 99 sin 100 rin 101 acin 102 extsmi 103 sus /res 104 gnd 201 x32in 200 199 jtagen 198 irq14 [lcddl2] 197 mcs16 [lcddl1] 196 iocs16 [lcddl0] 189 177 lcdd2 (iochchk /iochchk ) 176 vcc1 175 lcdd1 (drq5/drq5) 174 lcdd3 (drq1/drq1) 171 dsmd6 (d/c /drq0) sa2 rc sa1 memw x1out [baud out] rstdrv connection diagram 14 lan?sc300 microcontroller data sheet preliminary lansc300 microcontroller pin designations this section, beginning with the connection diagram on the preceding page, identifies the pins of the lansc300 microcontroller and lists the signals associ- ated with each pin. the table beginning on page 15 lists the pins sorted by pin number; the table beginning on page 17 lists the pins sorted by pin name along with the corresponding pin number, functional grouping, pin state table number, and the page number where a de- scription of the pin is located. tables 2C11, beginning on page 25, group these signals according to function. the signal name column in the pin designation table (sorted by pin number), and in tables 2C11, is decoded as follows: name1 / name2 [name3] (name4 / name5) name1 - this is the pin function when the lansc300 microcontroller has been configured, at reset, for the internal lcd controller mode of operation. if the pin only has one function regardless of the mode, name1 is the only name given. name2 - this is the secondary pin function (by default) when the lansc300 microcontroller has been config- ured, at reset, for the internal lcd controller mode of operation. if the pin always has two functions regard- less of the mode, name1 followed by name2 are the only names given. name3 - this is a tertiary pin function that must be en- abled specifically by firmware. as an example, for pins dack2 [tck], drq2[tdo], aen[tdi], and tc[tms], the name3 function is selected by the jtagen pin being asserted high (jtag enable). name4 - designates the pin function when the lansc300 microcontroller has been configured, at re- set, for the local bus mode of operation. name5 - designates the pin function when the lansc300 microcontroller has been configured, at re- set, for the maximum isa mode of operation. rsvd - pins marked with this designator are required to remain unconnected. pullup - needs external pull-up resistor. pulldn - needs external pull-down resistor. the signal name column in the pin designation table (sorted by pin name), beginning on page 17, contains an alphabetical listing of all pin names, followed by their corresponding alternate pin names in the applica- ble format from those listed here: name1 / name2 [name3] (name4 / name5) name2 / name1 [name3] (name4 / name5) [name3] (name4 / name5) name1 / name2 (name4 / name5) name1 / name2 [name3] (name5 / name4) name1 / name2 [name3] for more information about how pins are shared and which functions are available in each bus mode, see alternate pin functions on page 68. lan?sc300 microcontroller data sheet 15 preliminary pin designations (sorted by pin number) pin no. signal name (alternate functions) pin no. signal name (alternate functions) pin no. signal name (alternate functions) 1 gnd 44 romcs 87 slct 2 ras0 45 sysclk [xtclk] 88 ack 3 ras1 46 dack2 [tclk] 89 init [pcmcwe ] 4 cas1l [srcs2 ] 47 aen [tdi] 90 ppdwe [ppdcs ] 5 cas1h [srcs3 ] 48 vsys 91 ppoen 6 cas0l [srcs0 ] 49 tc [tms] 92 dtr /cfg1 7 cas0h [srcs1 ] 50 endirl 93 rts /cfg0 8mwe 51 endirh 94 sout 9 vmem 52 gnd 95 vcc5 10 ma10/sa13 53 gnd 96 cts 11 ma9/sa23 54 ior 97 dsr 12 gnd 55 iow 98 dcd 13 ma8/sa22 56 memr 99 sin 14 ma7/sa21 57 memw 100 rin 15 ma6/sa20 58 rstdrv 101 acin 16 ma5/sa19 59 dbufoe 102 extsmi 17 ma4/sa18 60 ma11/sa12 103 sus /res 18 ma3/sa17 61 sa11 104 gnd 19 ma2/sa16 62 sa10 105 gnd 20 gnd 63 sa9 106 bl1 21 ma1/sa15 64 sa8 107 bl2 22 vmem 65 vsys 108 bl3 23 vcc 66 sa7 109 bl4 24 ma0/sa14 67 sa6 110 cd_a 25 d15 68 gnd 111 rdy_a 26 d14 69 sa5 112 wp_a 27 d13 70 sa4 113 bvd2_a 28 d12 71 sa3 114 bvd1_a 29 d11 72 sa2 115 wait_ab 30 d10 73 sa1 116 cd_b 31 d9 74 sa0 117 rdy_b 32 d8 75 8042cs [xtdat] 118 wp_b 33 gnd 76 drq2 [tdo] 119 bvd2_b 34 d7 77 pmc2 120 bvd1_b 35 vmem 78 rc 121 gnd 36 d6 79 a20gate 122 icdir 37 d5 80 afdt [x14out] 123 mcel_b 38 d4 81 vcc 124 mceh_b 39 d3 82 pe 125 vpp_b 40 d2 83 strb 126 reg_b 41 d1 84 slctin [pcmcoe ]127rst_b 42 d0 85 busy 128 vcc5 43 doscs 86 error 129 mcel_a 16 lan?sc300 microcontroller data sheet preliminary pin no. signal name (alternate functions) pin no. signal name (alternate functions) pin no. signal name (alternate functions) 130 mceh_a 157 gnd 184 pmc4 131 vpp_a 158 dsma7 (a16/dack0 )185pmc3 132 reg_a 159 dsma6 (a15/dack3 ) 186 pgp3 133 rst_a 160 dsma5 (a14/dack7 ) 187 pgp2 134 ca24 161 dsma4 (a13/dack6 ) 188 pgp1 135 vcc 162 dsma3 (cpuclk/pullup) 189 pgp0 136 ca25 163 dsma2 (cpurst/rsvd) 190 lph 137 pmc0 164 dsma1 (pullup/irq7) 191 gnd 138 pmc1 165 dsma0 (nc/pullup) 192 iochrdy 139 spkr 166 dsmd1 (lrdy /drq6) 193 pirq1 (pirq1/irq6) 140 ioreset 167 dsmd2 (ble /irq11) 194 pirq0 (pirq0/irq3) 141 resin 168 dsmd3 (bhe /irq9) 195 irq1 142 vsys2 169 dsmd4 (w/r /drq7) 196 iocs16 [lcddl0] 143 sbhe [lcddl3] 170 dsmd5 (m/io /drq3) 197 mcs16 [lcddl1] 144 lcdd0 (dack5 /dack5 ) 171 dsmd6 (d/c /drq0) 198 irq14 [lcddl2] 145 lvdd (a12/bale) 172 dsmd7 (ads /0ws ) 199 jtagen 146 dsce (dack1 / dack1 ) 173 m (irq4/irq4) 200 x1out [baud_out] 147 dsoe (cpurdy /lmeg ) 174 lcdd3 (drq1/drq1) 201 x32in 148 dsmd0 (ldev /rsvd) 175 lcdd1 (drq5/drq5) 202 x32out 149 dsma14 (a23/la23) 176 vcc1 203 avcc 150 dsma13 (a22/la22) 177 lcdd2 (iochchk / iochchk ) 204 lf1 151 dsma12 (a21/la21) 178 cp1 (pulldn/irq5) 205 lf2 152 dsma11 (a20/la20) 179 cp2 (pullup/irq10) 206 lf3 153 dsma10 (a19/la19) 180 vcc 207 lf4 154 dsma9 (a18/la18) 181 frm (irq12/irq12) 208 agnd 155 dsma8 (a17/la17) 182 lvee (irq15/irq15) - - 156 gnd 183 dswe (pullup/pullup) - - pin designations (sorted by pin number) (continued) lan?sc300 microcontroller data sheet 17 preliminary pin designations (sorted by pin name) signal name (alternate functions) pin no. functional group pin state table number description page number (0 ws /ads ) dsmd7 172 maximum isa bus interface 8 43 8042cs [xtdat] 75 keyboard interface 3 37 (a12/bale) lvdd 173 local bus interface 8 42 (a13/dack6 ) dsma4 161 local bus interface 8 42 (a14/dack7 ) dsma5 160 local bus interface 8 42 (a15/dack3 ) dsma6 159 local bus interface 8 42 (a16/dack0 ) dsma7 158 local bus interface 8 42 (a17/la17) dsma8 155 local bus interface 8 42 (a18/la18) dsma9 154 local bus interface 8 42 (a19/la19) dsma10 153 local bus interface 8 42 (a20/la20) dsma11 152 local bus interface 8 42 a20gate 79 keyboard interface 3 37 (a21/la21) dsma12 151 local bus interface 8 42 (a22/la22) dsma13 150 local bus interface 8 42 (a23/la23) dsma14 149 local bus interface 8 42 acin 101 power management interface 6 40 ack 88 parallel port interface 4 37 (ads /0ws ) dsmd7 172 local bus interface 8 42 aen [tdi] 47 system interface 2 35 afdt [x14out] 80 parallel port interface 4 37 agnd 208 power 10 44 avcc 203 power 10 44 (bale/a12) lvdd 173 maximum isa bus interface 8 43 [baud_out] x1out 200 miscellaneous interface 9 42 (bhe /irq9) dsmd3 168 local bus interface 8 42 bl1 106 power management interface 6 40 bl2 107 power management interface 6 40 bl3 108 power management interface 6 40 bl4 109 power management interface 6 40 (ble /irq11) dsmd2 167 local bus interface 8 42 busy 85 parallel port interface 4 37 bvd1_a (stschg_a ) 114 pcmcia interface 7 38 bvd1_b (stschg_b ) 120 pcmcia interface 7 38 bvd2_a (spkr_a ) 113 pcmcia interface 7 38 bvd2_b (spkr_b ) 119 pcmcia interface 7 38 ca24 134 pcmcia interface 7 38 ca25 136 pcmcia interface 7 38 cas0h [srcs1 ] 7 memory bus interface 1 34 cas0l [srcs0 ] 6 memory bus interface 1 34 cas1h [srcs3 ] 5 memory bus interface 1 34 cas1l [srcs2 ] 4 memory bus interface 1 34 cd_a 110 pcmcia interface 7 38 18 lan?sc300 microcontroller data sheet preliminary signal name (alternate functions) pin no. functional group pin state table number description page number cd_b 116 pcmcia interface 7 38 cfg0/rts 93 serial port interface 5 38 cfg1/dtr 92 serial port interface 5 38 cp1 (pulldn/irq5) 178 display interface 8 41 cp2 (pullup/irq10) 179 display interface 8 41 (cpuclk/pullup) dsma3 162 local bus interface 8 43 (cpurdy /lmeg ) dsoe 147 local bus interface 8 43 (cpurst/rsvd) dsma2 163 local bus interface 8 43 cts 96 serial port interface 5 38 d0 42 system interface 2 35 d1 41 system interface 2 35 d10 30 system interface 2 35 d11 29 system interface 2 35 d12 28 system interface 2 35 d13 27 system interface 2 35 d14 26 system interface 2 35 d15 25 system interface 2 35 d2 40 system interface 2 35 d3 39 system interface 2 35 d4 38 system interface 2 35 d5 37 system interface 2 35 d6 36 system interface 2 35 d7 34 system interface 2 35 d8 32 system interface 2 35 d9 31 system interface 2 35 (d ack0 /a16) dsma7 158 maximum isa bus interface 8 43 (dack1 /dack1 ) dsce 146 local and maximum isa bus interface 8 43 dack2 [tck] 46 system and maximum isa bus interface 2 35, 44 (d ack3 /a15) dsma6 159 maximum isa bus interface 8 43 (dack5 /dack5 ) lcdd0 144 local and maximum isa bus interface 8 43 (d ack6 /a13) dsma4 161 maximum isa bus interface 8 43 (d ack7 /a14) dsma5 160 maximum isa bus interface 8 43 dbufoe 59 system interface 2 35 (d/c /drq0) dsmd6 171 local bus interface 8 43 dcd 98 serial port interface 5 38 doscs 43 memory bus interface 1 34 (drq0/d/c) dsmd6 171 maximum isa bus interface 8 43 (drq1/drq1) lcdd3 174 local and maximum isa bus interface 8 43 drq2 [tdo] 76 system and maximum isa bus interface 2 35, 44 (drq3/m/io ) dsmd5 170 maximum isa bus interface 8 43 (drq5/drq5) lccd1 175 local and maximum isa bus interface 8 43 (drq6/lrdy ) dsmd1 166 maximum isa bus interface 8 43 (drq7/w/r ) dsmd4 169 maximum isa bus interface 8 43 pin designations (sorted by pin name) (continued) lan?sc300 microcontroller data sheet 19 preliminary signal name (alternate functions) pin no. functional group pin state table number description page number dsce (dack1 /dack1 ) 146 display interface 8 41 dsma0 (nc/pullup) 165 display interface 8 41 dsma1 (pullup/irq7) 164 display interface 8 41 dsma10 (a19/la19) 153 display interface 8 41 dsma11 (a20/la20) 152 display interface 8 41 dsma12 (a21/la21) 151 display interface 8 41 dsma13 (a22/la22) 150 display interface 8 41 dsma14 (a23/la23) 149 display interface 8 41 dsma2 (cpurst/rsvd) 163 display interface 8 41 dsma3 (cpuclk/pullup) 162 display interface 8 41 dsma4 (a13/dack6 ) 161 display interface 8 41 dsma5 (a14/dack7 ) 160 display interface 8 41 dsma6 (a15/dack3 ) 159 display interface 8 41 dsma7 (a16/dack0 ) 158 display interface 8 41 dsma8 (a17/la17) 155 display interface 8 41 dsma9 (a18/la18) 154 display interface 8 41 dsmd0 (ldev /rsvd) 148 display interface 8 41 dsmd1 (lrdy /drq6) 166 display interface 8 41 dsmd2 (ble /irq11) 167 display interface 8 41 dsmd3 (bhe /irq9) 168 display interface 8 41 dsmd4 (w/r /drq7) 169 display interface 8 41 dsmd5 (m/io /drq3) 170 display interface 8 41 dsmd6 (d/c /drq0) 171 display interface 8 41 dsmd7 (ads /0ws ) 172 display interface 8 41 dsoe (cpurdy /lmeg ) 147 display interface 8 41 dsr 97 serial port interface 5 38 dswe (pullup/pullup) 183 display interface 8 41 dtr /cfg1 92 serial port interface 5 38 endirh 51 system interface 2 35 endirl 50 system interface 2 35 error 86 parallel port interface 4 37 extsmi 102 power management interface 6 40 frm (irq12/irq12) 181 display interface 8 41 gnd 1, 12, 20, 33, 52, 53, 68, 104, 105, 121, 156, 157, 191 power 10 45 icdir 122 pcmcia interface 7 39 init [pcmcwe ] 89 parallel port interface 4 37 (iochchk /iochchk ) 177 maximum isa bus interface 8 43 iochrdy 192 system interface 2 35 iocs16 [lcddl0] 196 system interface 8 35 pin designations (sorted by pin name) (continued) 20 lan?sc300 microcontroller data sheet preliminary signal name (alternate functions) pin no. functional group pin state table number description page number (iois16a ) wp_a 112 pcmcia interface 7 39 (iois16b ) wp_b 118 pcmcia interface 7 39 ior 54 system interface 2 35 ioreset 140 reset and power 9 45 iow 55 system interface 2 36 (ireq_a ) rdy_a 111 pcmcia interface 7 39 (ireq_b ) rdy_b 117 pcmcia interface 7 39 irq1 195 system and maximum isa bus interface 2 36, 44 (irq10/pullup) cp2 179 maximum isa bus interface 8 44 (irq11/ble ) dsmd2 167 maximum isa bus interface 8 44 (irq12/irq12) frm 181 local and maximum isa bus interface 8 44 irq14 [lcddl2] 198 system and maximum isa bus interface 8 36, 44 (irq15/irq15) lvee 182 local and maximum isa bus interface 8 44 (irq3/pirq0) pirq0 194 maximum isa bus interface 2 44 (irq4/irq4) m 173 local and maximum isa bus interface 8 44 (irq5/pulldn) cp1 178 maximum isa bus interface 8 44 (irq6/pirq1) pirq1 193 maximum isa bus interface 2 44 (irq7/pullup) dsma1 164 maximum isa bus interface 8 44 (irq9/bhe ) dsmd3 168 maximum isa bus interface 8 44 jtagen 199 jtag boundary scan interface 9 44 (la17/a17) dsma8 155 maximum isa bus interface 8 44 (la18/a18) dsma9 154 maximum isa bus interface 8 44 (la19/a18) dsma10 153 maximum isa bus interface 8 44 (la20/a20) dsma11 152 maximum isa bus interface 8 44 (la21/a21) dsma12 151 maximum isa bus interface 8 44 (la22/a22) dsma13 150 maximum isa bus interface 8 44 (la23/a23) dsma14 149 maximum isa bus interface 8 44 lcdd0 (dack5 /dack5 ) 144 display interface 8 41 lcdd1 (drq5/drq5) 175 display interface 8 41 lcdd2 (iochchk /iochchk ) 177 display interface 8 41 lcdd3 (drq1/drq1) 174 display interface 8 41 [lcddl0] iocs16 196 display interface 8 35 [lcddl1] mcs16 197 display interface 8 36 [lcddl2] irq14 198 display interface 8 36 [lcddl3] sbhe 143 display interface 8 36 (ldev /rsvd) dsmd0 148 local bus interface 8 43 lf1 204 miscellaneous interface 9 42 lf2 205 miscellaneous interface 9 42 lf3 206 miscellaneous interface 9 42 lf4 207 miscellaneous interface 9 42 (l meg /cpurdy ) dsoe 147 maximum isa bus interface 8 44 lph 190 power management interface 6 40 (lrdy /drq6) dsmd1 166 local bus interface 8 43 pin designations (sorted by pin name) (continued) lan?sc300 microcontroller data sheet 21 preliminary signal name (alternate functions) pin no. functional group pin state table number description page number lvdd (a12/bale) 173 display interface 8 41 lvee (irq15/irq15) 182 display interface 8 41 m (irq4/irq4) 173 display interface 8 42 ma0/sa14 24 memory bus interface 1 34 ma1/sa15 21 memory bus interface 1 34 ma10/sa13 10 memory bus interface 1 34 ma11/sa12 60 memory bus interface 1 34 ma2/sa16 19 memory bus interface 1 34 ma3/sa17 18 memory bus interface 1 34 ma4/sa18 17 memory bus interface 1 34 ma5/sa19 16 memory bus interface 1 34 ma6/sa20 15 memory bus interface 1 34 ma7/sa21 14 memory bus interface 1 34 ma8/sa22 13 memory bus interface 1 34 ma9/sa23 11 memory bus interface 1 34 mceh_a 130 pcmcia interface 7 39 mceh_b 124 pcmcia interface 7 39 mcel_a 129 pcmcia interface 7 39 mcel_b 123 pcmcia interface 7 39 mcs16 [lcddl1] 197 system interface 8 36 memr 56 system interface 2 36 memw 57 system interface 2 36 (m/io /drq3) dsmd5 170 display interface 8 41 mwe 8 memory bus interface 1 34 [pcmcoe ] slctin 84 pcmcia interface 4 38 [pcmcwe ] init 89 pcmcia interface 4 39 pe 82 parallel port interface 4 37 pgp0 189 power management interface 6 40 pgp1 188 power management interface 6 40 pgp2 187 power management interface 6 40 pgp3 186 power management interface 6 40 pirq0 (pirq0/irq3) 194 system and maximum isa bus interface 2 36, 44 (pirq0/irq3) pirq0 194 system and maximum isa bus interface 2 36, 44 pirq1 (pirq1/irq6) 193 system and maximum isa bus interface 2 36, 44 (pirq1/irq6) pirq1 193 system and maximum isa bus interface 2 36, 44 pmc0 137 power management interface 6 40 pmc1 138 power management interface 6 40 pmc2 77 power management interface 6 40 pmc3 185 power management interface 6 40 pmc4 184 power management interface 6 40 [ppdcs ] ppdwe 90 parallel port interface 4 37 ppdwe [ppdcs ] 90 parallel port interface 4 37 ppoen 91 parallel port interface 4 37 pin designations (sorted by pin name) (continued) 22 lan?sc300 microcontroller data sheet preliminary signal name (alternate functions) pin no. functional group pin state table number description page number ras0 2 memory bus interface 1 34 ras1 3 memory bus interface 1 34 rc 78 keyboard interface 3 37 rdy_a (ireq_a ) 111 pcmcia interface 7 39 rdy_b (ireq_b ) 117 pcmcia interface 7 39 reg_a 132 pcmcia interface 7 39 reg_b 126 pcmcia interface 7 39 resin 141 reset and power 9 45 rin 100 serial port interface 5 38 romcs 44 memory bus interface 1 34 rst_a 133 pcmcia interface 7 39 rst_b 127 pcmcia interface 7 39 rstdrv 58 system interface 2 36 rts /cfg0 93 serial port interface 5 38 sa0 74 system interface 2 36 sa1 73 system interface 2 36 sa10 62 system interface 2 36 sa11 61 system interface 2 36 sa12 60 system interface 2 34 sa13/ma10 10 system interface 1 34 sa14/ma0 24 system interface 1 34 sa15/ma1 21 system interface 1 34 sa16/ma2 19 system interface 1 34 sa17/ma3 18 system interface 1 34 sa18/ma4 17 system interface 1 34 sa19/ma5 16 system interface 1 34 sa2 72 system interface 2 36 sa20/ma6 15 system interface 1 34 sa21/ma7 14 system interface 1 34 sa22/ma8 13 system interface 1 34 sa23/ma9 11 system interface 1 34 sa3 71 system interface 2 36 sa4 70 system interface 2 36 sa5 69 system interface 2 36 sa6 67 system interface 2 36 sa7 66 system interface 2 36 sa8 64 system interface 2 36 sa9 63 system interface 2 36 sbhe [lcddl3] 143 system interface 8 36 sin 99 serial port interface 5 38 slct 87 parallel port interface 4 37 slctin [pcmcoe ] 84 parallel port interface 4 38 sout 94 serial port interface 5 38 pin designations (sorted by pin name) (continued) lan?sc300 microcontroller data sheet 23 preliminary signal name (alternate functions) pin no. functional group pin state table number description page number spkr 139 miscellaneous interface 9 36 (spkr_a ) bvd2_a 113 pcmcia interface 7 38 (spkr_b ) bvd2_b 119 pcmcia interface 7 38 [srcs0 ] cas0l 6 memory bus interface 1 34 [srcs1 ] cas0h 7 memory bus interface 1 34 [srcs2 ] cas1l 4 memory bus interface 1 34 [srcs3 ] cas1h 5 memory bus interface 1 34 strb 83 parallel port interface 4 38 (stschg_a ) bvd1_a 114 pcmcia interface 7 38 (stschg_b ) bvd1_b 120 pcmcia interface 7 38 sus /res 103 power management interface 6 40 sysclk [xtclk] 45 system interface 2 37 tc [tms] 49 system interface 2 37 [tck] dack2 46 jtag boundary scan interface 2 44 [tdi] aen 47 jtag boundary scan interface 2 44 [tdo] drq2 76 jtag boundary scan interface 2 44 [tms] tc 49 jtag boundary scan interface 2 44 vcc 23, 81, 135, 180 power 10 45 vcc1 176 power 10 45 vcc5 95, 128 power 10 45 vmem 9, 22, 35 power 10 45 vpp_a 131 pcmcia interface 7 39 vpp_b 125 pcmcia interface 7 39 vsys 48, 65 power 10 45 vsys2 142 power 10 45 (w/r /drq7) dsmd4 169 local bus interface 8 43 wait_ab 115 pcmcia interface 7 39 wp_a (iois16a ) 112 pcmcia interface 7 39 wp_b (iois16b ) 118 pcmcia interface 7 39 x1out [baud_out] 200 miscellaneous interface 9 42 [x14out] afdt 80 miscellaneous and parallel port interface 4 37, 42 x32in 201 miscellaneous interface 9 42 x32out 202 miscellaneous interface 9 42 [xtclk] sysclk 45 system and keyboard interface 2 37 [xtdat] 8042cs 75 keyboard interface 3 37 pin designations (sorted by pin name) (continued) 24 lan?sc300 microcontroller data sheet preliminary pin state tables the pin state tables beginning on page 25 are grouped by function based on their primary function when the lansc300 microcontroller is configured at reset for the internal lcd controller mode (name1). see page 14 for a description of name1. the pin state ta- bles also show the i/o type and reset state for those pins that have been configured at reset for either local bus mode or maximum isa bus mode. pin characteristics the following information clarifies the meaning of the pin state tables beginning on page 25: the letters in the i/o type column of tables 1C10 mean the following: i C input oCoutput sti C schmitt trigger input b C bidirectional aCanalog the term column refers to internal termination. the letters in this column of tables 1C10 mean the follow- ing: pd C pull-down resistor pu C pull-up resistor the symbols (letters) in the drive type column specify the drive capability of output pins. these specifications can be found in the dc characteristics section begin- ning on page 80 of this document. for a more complete description of i/o drive types, see derating curves on page 84 and table 48 on page 84. the clock off column describes the logic level of the i/o pins while the lansc300 microcontroller is in any of the power management modes where the cpu clock is stopped, and power is still applied to both the vccio and vcc clamp supply pins associated with that i/o pin. for doze mode, the data reflects a situation in which the internal cga controller video refresh is dis- abled. the reset state column lists the i/o pin voltage level when all of the vcc pins are stable and the resin input is active. the level of the vcc pins correlating to this data is shown in table 1. the vccio column refers to the voltage supply pin on the lansc300 microcontroller that is directly con- nected to the output driver for the specified signal pin. the vcc clamp column refers to the voltage supply pin on the lansc300 microcontroller that is directly connected to the esd protection diode (cathode) for the specified signal pin. any pin with a 5-v vcc clamp is a 5-v safe input. the spec. load (specification load) column is used to determine derated ac timing. see derating curves on page 84 of this data sheet. table 1. i/o pin voltage level internal cga (v) local bus (v) maximum isa (v) vcc 3.3 3.3 3.3 avcc 3.3 3.3 3.3 vcc5 5.0 5.0 5.0 vsys2 3.3 3.3 5.0 vsys 5.0 5.0 5.0 vmem 3.3 3.3 3.3 vcc1 3.3 3.3 3.3 lan?sc300 microcontroller data sheet 25 preliminary notes: 1. these signals are active during reset. 2. these pins always default to their dram interface function. 3. the drive strength for these pins is programmable. e is the default. all inputs that have vcc clamp = 5 v are 5-v safe inputs regardless of their vccio. table 2. memory bus interface signal name pin no. i/o type term drive type reset state (volts) vcc clamp spec. load (pf) clock off internal cga local bus max isa vccio ras0 1,3 2 o e,d,c active 3.3/0 3.3/0 3.3/0 vmem vmem 50 ras1 1,3 3 o e,d,c active 3.3/0 3.3/0 3.3/0 vmem vmem 50 cas1l [srcs2 ] 1,2 4 o d active 3.3/0 3.3/0 3.3/0 vmem vmem 30 cas1h [srcs3] 1,2 5 o d active 3.3/0 3.3/0 3.3/0 vmem vmem 30 cas0l [srcs0 ] 1,2 6 o d active 3.3/0 3.3/0 3.3/0 vmem vmem 30 cas0h [srcs1 ] 1,2 7 o d active 3.3/0 3.3/0 3.3/0 vmem vmem 30 ma10/sa13 3 10 o e,d,c 0 3.3 3.3 3.3 vmem vmem 70 ma9/sa23 3 11 o e,d,c 0 3.3 3.3 3.3 vmem vmem 70 ma8/sa22 3 13 o e,d,c 0 3.3 3.3 3.3 vmem vmem 70 ma7/sa21 3 14 o e,d,c 0 3.3 3.3 3.3 vmem vmem 70 ma6/sa20 3 15 o e,d,c 0 3.3 3.3 3.3 vmem vmem 70 ma5/sa19 3 16 o e,d,c 0 3.3 3.3 3.3 vmem vmem 70 ma4/sa18 3 17 o e,d,c 0 3.3 3.3 3.3 vmem vmem 70 ma3/sa17 3 18 o e,d,c 0 3.3 3.3 3.3 vmem vmem 70 ma2/sa16 3 19 o e,d,c 0 3.3 3.3 3.3 vmem vmem 70 ma1/sa15 3 21 o e,d,c 0 3.3 3.3 3.3 vmem vmem 70 ma0/sa14 3 24 o e,d,c 0 3.3 3.3 3.3 vmem vmem 70 mwe 3 8 o e,d,c 1 3.3 3.3 3.3 vmem vmem 70 romcs 44 o b 1 5.0 5.0 5.0 vsys v cc 5 30 doscs 43 o b 1 5.0 5.0 5.0 vsys v cc 5 50 26 lan?sc300 microcontroller data sheet preliminary table 3. system interface signal name pin no. i/o type term drive type clock off reset state (volts) vccio vcc clamp spec. load (pf) internal cga local bus max isa ma11/sa12 60 o e 0 5.0 5.0 5.0 vsys vcc5 70 sa11 61 o d 0 5.0 5.0 5.0 vsys vcc5 70 sa10 62 o d 0 5.0 5.0 5.0 vsys vcc5 70 sa9 63 o d 0 5.0 5.0 5.0 vsys vcc5 70 sa8 64 o d 0 5.0 5.0 5.0 vsys vcc5 70 sa7 66 o d 0 5.0 5.0 5.0 vsys vcc5 70 sa6 67 o d 0 5.0 5.0 5.0 vsys vcc5 70 sa5 69 o d 0 5.0 5.0 5.0 vsys vcc5 70 sa4 70 o d 0 5.0 5.0 5.0 vsys vcc5 70 sa3 71 o d 0 5.0 5.0 5.0 vsys vcc5 70 sa2 72 o d 0 5.0 5.0 5.0 vsys vcc5 70 sa1 73 o d 0 5.0 5.0 5.0 vsys vcc5 70 sa0 74 o d 0 0.0 0.0 0.0 vsys vcc5 70 d15 2 25 b pd e,d,c 0 0.0 0.0 0.0 vmem vmem 70 d14 2 26 b pd e,d,c 0 0.0 0.0 0.0 vmem vmem 70 d13 2 27 b pd e,d,c 0 0.0 0.0 0.0 vmem vmem 70 d12 2 28 b pd e,d,c 0 0.0 0.0 0.0 vmem vmem 70 d11 2 29 b pd e,d,c 0 0.0 0.0 0.0 vmem vmem 70 d10 2 30 b pd e,d,c 0 0.0 0.0 0.0 vmem vmem 70 d9 2 31 b pd e,d,c 0 0.0 0.0 0.0 vmem vmem 70 d8 2 32 b pd e,d,c 0 0.0 0.0 0.0 vmem vmem 70 d7 2 34 b pd e,d,c 0 0.0 0.0 0.0 vmem vmem 70 d6 2 36 b pd e,d,c 0 0.0 0.0 0.0 vmem vmem 70 d5 2 37 b pd e,d,c 0 0.0 0.0 0.0 vmem vmem 70 d4 2 38 b pd e,d,c 0 0.0 0.0 0.0 vmem vmem 70 d3 2 39 b pd e,d,c 0 0.0 0.0 0.0 vmem vmem 70 d2 2 40 b pd e,d,c 0 0.0 0.0 0.0 vmem vmem 70 d1 2 41 b pd e,d,c 0 0.0 3.3 0.0 vmem vmem 70 d0 2 42 b pd e,d,c 0 0.0 3.3 0.0 vmem vmem 70 sysclk [xtclk] 1 45 o(sti) b 0(C) 5.0/0 5.0/0 5.0/0 vsys vcc5 30 irq1 195 i pu C C 4.4 4.4 4.4 vcc1 vcc5 pirq1 (pirq1/irq6) 193 i pu C(C/C) C(C/C) 3.3 3.3 3.3 vcc1 vcc5 pirq0(pirq0/irq3) 194 i pu C(C/C) C(C/C) 3.3 3.3 3.3 vcc1 vcc5 dack2 [tck] 46 o(i) b 1 5.0 5.0 5.0 vsys vcc5 30 drq2 [tdo] 76 i(o) pd a C 0.0 0.0 0.0 vsys vcc5 30 lan?sc300 microcontroller data sheet 27 preliminary notes: 1. reset state sysclk frequency is 4.6 mhz. 2. the drive strength for these pins is programmable. e is the default. all inputs that have vcc clamp = 5 v are 5-v safe inputs regardless of their vccio. aen [tdi] 47 o(i) b 1 0.0 0.0 0.0 vsys vcc5 30 tc [tms] 49 o(i) b 0 0.0 0.0 0.0 vsys vcc5 30 endirl 50 o b 1 5.0 5.0 5.0 vsys vcc5 30 endirh 51 o b 1 5.0 5.0 5.0 vsys vcc5 30 dbufoe 59 o b 1 5.0 5.0 5.0 vsys vcc5 30 ior 54 o c 1 5.0 5.0 5.0 vsys vcc5 50 iow 55 o c 1 5.0 5.0 5.0 vsys vcc5 50 memr 56 o c 1 5.0 5.0 5.0 vsys vcc5 50 memw 57 o c 1 5.0 5.0 5.0 vsys vcc5 50 rstdrv 58 o a 0 5.0 5.0 5.0 vsys vcc5 30 iochrdy 192 sti pu C C 3.3 3.3 3.3 vcc1 vcc5 iocs16 [lcddl0] 196 i [b] c C [0] 3.3 3.3 3.3 vcc1 vcc5 70 mcs16 [lcddl1] 197 i [b] c C [0] 3.3 3.3 3.3 vcc1 vcc5 70 irq14 [lcddl2] 198 i [b] c C [0] 0.0 0.0 0.0 vcc1 vcc5 70 sbhe [lcddl3] 143 o [b] c 0[0] 0.0 0.0 0.0 vsys2 vcc5 70 table 3. system interface (continued) signal name pin no. i/o type term drive type clock off reset state (volts) vccio vcc clamp spec. load (pf) internal cga local bus max isa 28 lan?sc300 microcontroller data sheet preliminary notes: all inputs that have vcc clamp = 5 v are 5-v safe inputs regardless of their vccio. notes: 1. these outputs function as open-drain outputs in normal parallel port mode, and function as cmos drivers when the epp- mode configuration bit is set. 2. the parallel port interface busy input must have an external pullup if the parallel port is to be used in epp mode. if this pullup is not present, accesses to the parallel port in epp mode will lock up the system. all inputs that have vcc clamp = 5 v are 5-v safe inputs regardless of their vccio. table 4. keyboard interface signal name pin no. i/o type term drive type clock off reset state (volts) vccio vcc clamp spec. load (pf) internal cga local bus max isa 8042cs [xtdat] 75 o(sti) b 1(C) 5.0 5.0 5.0 vsys vcc5 30 rc 78 i pu C C 5.0 5.0 5.0 vsys vcc5 a20gate 79 i pu C C 5.0 5.0 5.0 vsys vcc5 table 5. parallel port interface signal name pin no. i/o type term drive type clock off reset state (volts) vccio vcc clamp spec. load (pf) internal cga local bus max isa afdt [x14out] 1 80 o d last state 5.0 5.0 5.0 vcc5 vcc5 100 init [pcmcwe ] 1 89 o d last state 0.0 0.0 0.0 vcc5 vcc5 100 strb 1 83 o d last state 5.0 5.0 5.0 vcc5 vcc5 100 slctin [pcmcoe ] 1 84 o d last state 5.0 5.0 5.0 vcc5 vcc5 100 ack 88 i C C 5.0 5.0 5.0 vcc5 vcc5 busy 2 85 i C C 5.0 5.0 5.0 vcc5 vcc5 error 86 i C C 5.0 5.0 5.0 vcc5 vcc5 pe 82 i C C 5.0 5.0 5.0 vcc5 vcc5 slct 87 i C C 5.0 5.0 5.0 vcc5 vcc5 ppdwe [ppdcs ] 90 o b 1(1) 5.0 5.0 5.0 vcc5 vcc5 30 ppoen 91 o b 1(1) 0.0 0.0 0.0 vcc5 vcc5 30 lan?sc300 microcontroller data sheet 29 preliminary notes: 1. these pins are terminated externally per bus option selection. all inputs that have vcc clamp = 5 v are 5-v safe inputs regardless of their vccio. notes: 1. pmc outputs: four low (pmc0, pmc1, pmc2, pmc4), one high (pmc3), default state after reset. all five are programmable as either active high or low after reset. all inputs that have vcc clamp = 5 v are 5-v safe inputs regardless of their vccio. table 6. serial port interface signal name pin no. i/o type term drive type clock off reset state (volts) vccio vcc clamp spec. load (pf) internal cga local bus max isa dtr /cfg 1 92 o a last state 0.0 5.0 0 vcc5 vcc5 50 rts /cfg0 1 93 o a last state 0.0 0.0 5.0 vcc5 vcc5 50 sout 94 o a last state 0.0 0.0 5.0 vcc5 vcc5 50 cts 96 i pu C 5.0 5.0 5.0 vcc5 vcc5 dcd 98 i pu C 5.0 5.0 5.0 vcc5 vcc5 dsr 97 i pu C 5.0 5.0 5.0 vcc5 vcc5 rin 100 i pu C 5.0 5.0 5.0 vcc5 vcc5 sin 99 i pu C 5.0 5.0 5.0 vcc5 vcc5 table 7. power management interface signal name pin no. i/o type term drive type clock off reset state (volts) vccio vcc clamp spec. load (pf) internal cga local bus max isa acin 101 sti pd C C 0.0 0.0 0.0 vcc5 vcc5 extsmi 102 sti pd C C 0.0 0.0 0.0 vcc5 vcc5 sus /res 103 sti C C 5.0 5.0 5.0 vcc5 vcc5 pmc4 1 184 o b active 0.0 0.0 0.0 vcc1 vcc5 50 pmc3 1 185 o b active 3.3 3.3 3.3 vcc1 vcc5 50 pmc2 1 77 o b active 0.0 0.0 0.0 vsys vcc5 50 pmc1 1 138 o b active 0.0 0.0 0.0 vcc5 vcc5 50 pmc0 1 137 o b active 0.0 0.0 0.0 vcc5 vcc5 50 pgp3 186 o b active 3.3 3.3 3.3 vcc1 vcc5 50 pgp2 187 o b active 3.3 3.3 3.3 vcc1 vcc5 50 pgp1 188 b b active 3.3 3.3 3.3 vcc1 vcc5 50 pgp0 189 b b active 0.0 0.0 0.0 vcc1 vcc5 50 bl1 106 sti C C 5.0 5.0 5.0 vcc5 vcc5 bl2 107 sti C C 5.0 5.0 5.0 vcc5 vcc5 bl3 108 sti C C 5.0 5.0 5.0 vcc5 vcc5 bl4 109 sti C C 5.0 5.0 5.0 vcc5 vcc5 lph 190 o b active 0.0 0.0 0.0 vcc1 vcc5 50 30 lan?sc300 microcontroller data sheet preliminary notes: 1. external weak pull-down resistor is required. 2. the reset state of these signals will be zero only if the reset state of the pcmcia power source is zero. all of these pins are required to be pulled up to the pcmcia power source externally. all inputs that have vcc clamp = 5 v are 5-v safe inputs regardless of their vccio. table 8. pcmcia interface signal name pin no. i/o type term drive type clock off reset state (volts) vccio vcc clamp spec. load (pf) internal cga local bus max isa mcel_a 129 o c 1 5.0 5.0 5.0 vcc5 vcc5 50 mceh_a 130 o c 1 5.0 5.0 5.0 vcc5 vcc5 50 vpp_a 131 o b active 0.0 0.0 0.0 vcc5 vcc5 50 reg_a 132 o b 0 5.0 5.0 5.0 vcc5 vcc5 50 rst_a 1 133 o b 3 state 0.0 0.0 0.0 vcc5 vcc5 50 cd_a 110 sti C C 5.0 5.0 5.0 vcc5 vcc5 rdy_a 2 111 i C C 0.0 0.0 0.0 vcc5 vcc5 wp_a 2 112 i C C 0.0 0.0 0.0 vcc5 vcc5 bvd2_a 2 113 sti C C 0.0 0.0 0.0 vcc5 vcc5 bvd1_a 2 114 sti C C 0.0 0.0 0.0 vcc5 vcc5 wait_ab 2 115 i C C 5.0 5.0 5.0 vcc5 vcc5 icdir 122 o c 1 5.0 5.0 5.0 vcc5 vcc5 50 mcel_b 123 o c 1 5.0 5.0 5.0 vcc5 vcc5 50 mceh_b 124 o c 1 5.0 5.0 5.0 vcc5 vcc5 50 vpp_b 125 o a active 0.0 0.0 0.0 vcc5 vcc5 50 reg_b 126 o a 0 5.0 5.0 5.0 vcc5 vcc5 50 rst_b 1 127 o b 3 state 0.0 0.0 0.0 vcc5 vcc5 50 cd_b 116 sti C C 5.0 5.0 5.0 vcc5 vcc5 rdy_b 2 117 i C C 0.0 0.0 0.0 vcc5 vcc5 wp_b 2 118 i C C 0.0 0.0 0.0 vcc5 vcc5 bvd2_b 2 119 sti C C 0.0 0.0 0.0 vcc5 vcc5 bvd1_b 2 120 sti C C 0.0 0.0 0.0 vcc5 vcc5 ca24 134 o b 0 0.0 0.0 0.0 vcc5 vcc5 50 ca25 136 o b 0 0.0 0.0 0.0 vcc5 vcc5 50 lan?sc300 microcontroller data sheet 31 preliminary table 9. display interface signal name pin no. i/o type term drive type clock off reset state (volts) vccio vcc clamp spec. load (pf) internal cga local bus max isa dsmd7 (ads /0ws ) 172 b (o/i) c 0 (1/C) 0.0 3.3 3.3 vcc1 vcc5 50 dsmd6 (d/c / drq0) 1 171 b (o/i) c 0 (ls/C) 0.0 3.3 0.0 vcc1 vcc5 50 dsmd5 (m/io / drq3) 1 170 b (o/i) c 0 (ls/C) 0.0 0.0 0.0 vcc1 vcc5 50 dsmd4 (w/r / drq7) 1 169 b (o/i) c 0 (ls/C) 0.0 0.0 0.0 vcc1 vcc5 50 dsmd3 (bhe / irq9) 1 168 b (o/i) c 0 (ls/C) 0.0 0.0 3.3 vcc1 vcc5 50 dsmd2 (ble / irq11) 1 167 b (o/i) c 0 (ls/C) 0.0 0.0 3.3 vcc1 vcc5 50 dsmd1 (lrdy / drq6) 166 b (i/i) c 0 (C/C) 0.0 0.0 0.0 vcc1 vcc5 50 dsmd0 (ldev / rsvd) 148 b (i/o) c 0 (C/3 state) 0.0 3.3 0.0 vsys2 vcc5 50 dsma14 (a23/ la23) 149 o c 0 3.3 3.3 5.0 vsys2 vcc5 50 dsma13 (a22/ la22) 150 o c 0 3.3 3.3 5.0 vsys2 vcc5 50 dsma12 (a21/ la21) 151 o c 0 3.3 3.3 5.0 vsys2 vcc5 50 dsma11 (a20/ la20) 152 o c 0 3.3 3.3 5.0 vsys2 vcc5 50 dsma10 (a19/ la19) 153 o c 0 3.3 3.3 5.0 vsys2 vcc5 50 dsma9 (a18/la18) 154 o c 0 3.3 3.3 5.0 vsys2 vcc5 50 dsma8 (a17/la17) 155 o c 0 3.3 3.3 5.0 vsys2 vcc5 50 dsma7 (a16/ dack0 ) 158 o c 0 (0/1) 3.3 3.3 5.0 vsys2 vcc5 50 dsma6 (a15/ dack3 ) 159 o c 0 (0/1) 3.3 3.3 5.0 vsys2 vcc5 50 dsma5 (a14/ dack7 ) 160 o c 0 (0/1) 3.3 3.3 5.0 vsys2 vcc5 50 dsma4 (a13/ dack6 ) 161 o c 0 (0/1) 3.3 3.3 5.0 vsys2 vcc5 50 dsma3 (cpuclk/ pullup) 2 162 o e 0 3.3 3.3/0 3.3 vcc1 vcc5 50 (30) dsma2 (cpurst/ rsvd) 163 o c 0 3.3 3.3 0.0 vcc1 vcc5 50 dsma1 (pullup/ irq7) 164 o (i/i) c 0 (C/C) 3.3 3.3 3.3 vcc1 vcc5 50 dsma0 (nc/ pullup) 165 o (0/i) c 0 (0/C) 0.0 3.3 3.3 vcc1 vcc5 50 dswe (pullup/ pullup) 183 o (i/i) b 1 (C/C) 3.3 3.3 3.3 vcc1 vcc5 30 dsoe (cpurdy/ lmeg) 147 o b 1 5.0 0.0 0.0 vsys2 vcc5 50 dsce (dack1 / dack1 ) 146 o b 1 0.0 3.3 5.0 vsys2 vcc5 30 32 lan?sc300 microcontroller data sheet preliminary notes: 1. ls in the clock off column stands for last state. 2. reset state local bus signal loading 920 mvC0 v. for 33-mhz operation, cpuclk loading = 30 pf. all inputs that have vcc clamp = 5 v are 5-v safe inputs regardless of their vccio. signal name pin no. i/o type term drive type clock off reset state (volts) vccio vcc clamp spec. load (pf) internal cga local bus max isa lcdd3 (drq1 / drq1) 174 o (i/i) c 0 (C/C) 0.0 0.0 0.0 vcc1 vcc5 100 lcdd0 (dack5 / dack5 ) 144 o c 0 (1/1) 3.3 3.3 5.0 vsys2 vcc5 100 lcdd1 (drq5/ drq5) 175 o (i/i) c 0 (C/C) 0.0 3.3 0.0 vcc1 vcc5 100 lcdd2 (iochchk / iochchk ) 177 o (i/i) c 0 (C/C) 0.0 3.3 3.3 vcc1 vcc5 100 m (irq4/irq4) 173 o (i/i) c 0 (C/C) 0.0 3.3 3.3 vcc1 vcc5 100 cp1 (pulldn/irq5) 178 o (i/i) c 0 (C/C) 0.0 0.0 3.3 vcc1 vcc5 100 cp2 (pullup/ irq10) 179 o (i/i) c 0 (C/C) 0.0 0.0 3.3 vcc1 vcc5 100 frm (irq12/irq12) 181 o (i/i) c 0 (C/C) 0.0 3.3 3.3 vcc1 vcc5 100 lvee (irq15/ irq15) 182 o (i/i) b 1 (C/C) 3.3 3.3 3.3 vcc1 vcc5 50 lvdd (a12/ bale) 145 o e 1(0/1) 3.3 3.3 5.0 vsys2 vcc5 50 iocs16 [lcddl0] 196 i [b] c C [0] 3.3 3.3 3.3 vcc1 vcc5 70 mcs16 [lcddl1] 197 i [b] c C [0] 3.3 3.3 3.3 vcc1 vcc5 70 irq14 [lcddl2] 198 i [b] c C [0] 0.0 0.0 0.0 vcc1 vcc5 70 sbhe [lcddl3] 143 o [b] c 0[0] 0.0 0.0 0.0 vsys2 vcc5 70 table 9. display interface (continued) lan?sc300 microcontroller data sheet 33 preliminary notes: 1. ioreset (pin #140) requires an external pull-down resistor (~10k). 2. reset state local bus signal and reset state isa max signal: 920 mvC0 v frequency = 32 khz. 3. reset state signal: 1.68 vC0 v frequency = 32 khz. 4. ls in the clock off column stands for last state. all inputs that have vcc clamp = 5 v are 5-v safe inputs regardless of their vccio. notes: 1. these reset state entries identify the vccio levels that are present on the lansc300 microcontroller for the three bus mode options. note that the device is not limited to these vcc levels. all inputs that have vcc clamp = 5 v are 5-v safe inputs regardless of their vccio. table 10. miscellaneous interface signal name pin no. i/o type term drive type clock off reset state (volts) vccio vcc clamp spec. load (pf) internal cga local bus max isa ioreset 1 140 i C C 0.0 0.0 0.0 vcc5 vcc5 x32in 2 201 i C C 640 mv 920/0 920/0 avcc avcc x32out 3 202 o osc. active 1.68/0 1.68/0 1.68/0 avcc avcc lf1 204 a C C 1.52 1.52 1.52 avcc avcc lf2 205 a C C 1.48 1.48 1.48 avcc avcc lf3 206 a C C 1.52 1.52 1.52 avcc avcc lf4 207 a C C 1.68 1.68 1.68 avcc avcc x1out [baud_out] 200 o b (ls) 4 0.0 1.24 1.24 vcc1 vcc5 50 resin 141 sti C C 0.0 0.0 0.0 vcc vcc spkr 4 139 o b (ls) 4 5.0 5.0 5.0 vcc5 vcc5 50 jtagen 199 i pd C C 0.0 0.0 0.0 vcc1 vcc5 table 11. power pins signal name pin no. i/o type term drive type clock off reset state (volts) vccio vcc clamp spec. load (pf) internal cga local bus max isa avcc 1 203 3.3 3.3 3.3 vcc 1 23, 81, 135,180 3.3 3.3 3.3 vcc5 1 95, 128 5.0 5.0 5.0 vsys2 1 142 3.3 3.3 5.0 vsys 1 48, 65 5.0 5.0 5.0 vmem 1 9, 22, 35 3.3 3.3 3.3 vcc1 1 176 3.3 3.3 3.3 gnd 1,12, 20, 33, 52, 53, 68, 104, 105, 121, 156, 157, 191 agnd 208 34 lan?sc300 microcontroller data sheet preliminary pin descriptions descriptions of the lansc300 microcontroller pins are organized into the following functional groupings: n memory bus interface n system interface n keyboard interface n parallel port interface n serial port interface n pcmcia interface n power management interface n display interface n miscellaneous interface n local bus interface n maximum isa bus interface n jtag boundary scan interface n reset and power memory bus interface cas1h [ srcs3 ], cas1l [ srcs2 ] , cas0h [ srcs1 ], cas0l [ srcs0 ] column address strobe (outputs; active low) column address strobe indicates to dram that a valid column address is present on the ma10Cma0 lines. two cas signals are allocated to each 16-bit bank, one per byte. when sram, instead of dram, is configured as main memory, srcs3 , srcs2 , srcs1 , and srcs0 are the alternate pin functions corresponding to cas1h , cas1l , cas0h , and cas0l respectively. each pin se- lects a byte in one of two possible 16-bit-wide sram banks. the sram functionality is selected via firm- ware. in this mode, all four of these outputs are active low. for more information about srcs3 C srcs0 , see page 49. doscs dos rom chip select (output; active low) the dos rom chip select is an active low output that provides the chip select function for the flash/rom array banks that are used to hold the operating system or application code. doscs is used to select the dos roms and can be configured to respond to direct ad- dressing or memory management system (mms) ad- dressing. ma11Cma0/sa23Csa12 memory address (outputs; active high) memory address lines for multiplexed and nonmulti- plexed memory devices; their effect depends on the system configuration and the type of bus cycle. n when system memory is configured as dram, the ma10Cma0 signals are multiplexed outputs and convey the row address during ras assertion and column address during cas assertion. n when system memory is configured as sram, ma11Cma0 output the system addresses, sa12C sa23, and are used in conjunction with sa1Csa11. n for cycles that are not targeted to system memory or internal i/o, ma11Cma0 are used to provide non- multiplexed isa-type address signals sa23Csa12, as shown in table 12. see also sa11Csa0 on page 36. m we write enable (output; active low) write enable is the write command strobe for the dram and sram devices. ras1 Cras0 row address strobe (output; active low) row address strobe indicates to dram that a valid row address is present on the ma11Cma0 lines. one ras signal is allocated for each 16-bit dram bank, one per word. romcs bios rom chip select (output; active low) bios rom chip select is an active low output that provides the chip select function for the flash/rom ar- ray. romcs is used to select the bios rom, and can be configured to respond to direct addressing or mms addressing. when configured for direct addressing, the bios rom can reside at one or all of the following ad- dress ranges: 0f0000hC0fffffh 0e0000hC0effffh 0d0000hC0dffffh 0c0000hC0cffffh 0a0000hC0affffh the bios rom chip select is also active for accesses into the 64-kbyte segment that contains the boot vec- tor, at address ff0000h to ffffffh. table 12. non-multiplexed address signals provided by ma11Cma0 ma11109876543210 sa 12 13 23 22 21 20 19 18 17 16 15 14 lan?sc300 microcontroller data sheet 35 preliminary for more information about the romcs pin, see the using 16-bit romcs designs in lan tm sc300 and lansc310 microcontrollers application note , order #21825. system interface aen [tdi] dma address enable (output; active high) aen is used to indicate that the current address active on the sa23Csa0 address bus is a memory address and that the current cycle is a dma cycle. all i/o de- vices should use this signal in decoding their i/o ad- dresses and should not respond when this signal is asserted. when aen is asserted, the dackx signals are used to select the appropriate i/o device for the dma transfer. this is a dual-function pin. when the jtagen signal is asserted, it functions as the tdi, jtag test data input pin. d15Cd0 system data bus (bidirectional; active high) the system data bus inputs data during memory and i/o read cycles, and outputs data during memory and i/o write cycles. during local bus and dram/sram cycles, this bus represents the cpu data bus. dack2 [tck] dma channel 2 acknowledge (output; active low) this output indicates that the current transfer is a dma transfer to the i/o device connected to this dma chan- nel. in pc-compatible system designs, this signal can be connected to the floppy disk controller dma ac- knowledge input. this is a dual-function pin. when the jtagen signal is asserted, it functions as the tck (jtag test clock) pin. see jtag boundary scan interface on page 44 for more information on the function of this pin during test mode. dbufoe data buffer output enable (output; active low) this output is used to control the output enable on the system data bus buffer. when low, the outputs of the data bus buffer are enabled. drq2 [tdo] dma channel 2 request (input; active high with internal pulldown) this input is used to request a dma transfer. it can be connected to the floppy disk controller dma request output in pc-compatible system designs. this is a dual-function pin. when the jtagen signal is asserted, it will function as the tdo, jtag test data out pin. see jtag boundary scan interface on page 44 for more information on the function of this pin dur- ing test mode. endirh high byte data buffer direction control (output; active high) this output controls the transceiver on the high byte of the data bus, bits 15C8. when asserted, this signal is used to enable the data from the lansc300 microcon- troller data bus to the buffered data bus. endirl low byte data buffer direction control (output; active high) this output controls the transceiver on the low byte of the data bus, bits 7C0. when asserted, this signal is used to enable the data from the lansc300 microcon- troller data bus to the buffered data bus. iochrdy i/o channel ready (input; active high) this signal is used by isa slave devices to add wait states to the current transfer. when this signal is deas- serted, wait states are added. iocs16 [lcddl0] (input; active low) this input is used to signal to the isa control logic that the targeted i/o device is a 16-bit device. (iocs16 is available unless the internal lcd controller bus mode is selected and a dual-scan lcd panel inter- face is selected via firmware.) iocs16 is generated by a 16-bit isa i/o expansion board when the board recognizes it is being ad- dressed. iocs16 provides the same function for 16-bit i/o expansion devices as the mcs16 signal provides for the 16-bit memory devices. note: iocs16 is internally ord with mcs16 . do not tie iocs16 low. for more information about the iocs16 pin, see the using 16-bit romcs designs in lan tm sc300 and lansc310 microcontrollers application note , order #21825. i or i/o read command (output; active low) the ior signal indicates that the current cycle is a read of the currently selected i/o device. when this signal is asserted, the selected i/o device can drive data onto the data bus. 36 lan?sc300 microcontroller data sheet preliminary iow i/o write command (output; active low) the iow signal indicates that the current cycle is a write of the currently selected i/o device. when this signal is asserted, the selected i/o device can latch data from the data bus. irq1, irq14 [lcddl2] interrupt request channels 1 and 14 (input; rising edge/active high, with internal pullup) this input is connected to the internal 8259a-compati- ble interrupt controller channels 1 and 14. in pc-com- patible systems, irq1 may be connected to the 8042 keyboard controller. (irq14 is available unless the internal lcd controller bus mode is selected and a dual-scan panel interface is selected via firmware.) m cs16 [lcddl1] (input; active low) this input is used to signal to the isa control logic that the targeted memory device is a 16-bit device. (mcs16 is available unless the internal lcd controller bus mode is selected and a dual-scan lcd panel inter- face is selected via firmware.) mcs16 is generated by a 16-bit memory expansion card when the card recognizes it is being addressed. this signal tells the data bus steering logic that the ad- dressed memory device is capable of communicating over both data paths. when accessing an 8-bit memory device, the mcs16 line remains deasserted, indicating to the data bus steering logic that the currently ad- dressed device is an 8-bit memory device capable of communicating only over the lower data path. note: mcs16 is internally ored with iocs16 . do not tie mcs16 low. for more information about the mcs16 pin, see the using 16-bit romcs designs in lan tm sc300 and lansc310 microcontrollers application note , order #21825. memr memory read command (output; active low) the memr signal indicates that the current cycle is a read of the currently selected memory device. when this signal is asserted, the selected memory device can drive data onto the data bus. memw memory write command (output; active low) the memw signal indicates that the current cycle is a write of the currently selected memory device. when this signal is asserted, the selected memory device can latch data from the data bus. pirq0 (pirq0/irq3), pirq1 (pirq1/irq6) programmable interrupt requests (inputs; rising edge/active high, with internal pullup) these two inputs can be programmed to drive any of the available interrupt controller interrupt request in- puts. for more information, see the pirq configura- tion register, index b2h, in the lan tm sc300 microcontroller programmers reference manual , order #18470. rstdrv system reset (output; active high) this signal is the isa-compatible reset signal. when this signal is asserted, all connected devices reinitialize to their reset state. the pulse width of rstdrv is ad- justable, based on pll startup timing. for more infor- mation, see loop filters on page 97 and the power- up sequence timings beginning on page 99. sa11Csa0 system address bus (output; active high) the system address bus outputs the physical memory or i/o port, least-significant, latched addresses. they are used by all external i/o devices and all memory de- vices other than main system dram. during main sys- tem sram and local bus cycles, this bus represents the cpu address bus (a11Ca1). sa0 is equivalent to a0 during local bus cycles. see ma11Cma0 on page 34 for sa23Csa12. sbhe [lcddl3] (output; active low) active when the high byte is to be transferred on the upper 8 bits of the data bus. (sbhe is available unless the internal lcd controller bus mode is selected and a dual-scan lcd panel inter- face is selected via firmware.) spkr speaker, digital audio output (output) this signal controls an external speaker driver. it is generated from the internal 8254-compatible timer channel 2 output anded with i/o port 061h, bit 1 (speaker data enable). lan?sc300 microcontroller data sheet 37 preliminary tc [tms] terminal count (output; active high) this signal is used to indicate that the transfer count for the currently active dma channel has reached zero, and that the current dma cycle is the last transfer. this is a dual-function pin. when the jtagen signal is asserted, it will function as the tms, jtag test mode select pin. see the jtag boundary scan interface on page 44 for more information on the function of this pin during test mode. keyboard interface 8 042cs [xtdat] keyboard controller chip select (output; active low) this signal is a decode of a9Ca0 = 060h to 06eh, all even addresses. in pc-compatible systems, it con- nects to the external keyboard controller chip select. xtdat is the pc/xt keyboard data line. a20gate address bit-20 gate (input; active high) when deasserted, this signal is used to force cpu ad- dress bit 20 low, a function required for pc compatibil- ity. in pc-compatible systems, this signal can be driven by an 8042 keyboard controller, port 2, bit 1. for detailed information about the a20gate signal, see the lan tm sc300 and lansc310 microcontrollers gatea20 function clarification application note, order #21811. rc reset cpu (input; active low) this signal resets the internal cpu. in pc-compatible systems, this signal can be driven by a keyboard con- troller, port 2, bit 0. sysclk [xtclk] system clock (output) this clock can be used to provide a clock to a keyboard controller. it is not synchronous to isa bus cycles. xtclk is the pc/xt keyboard clock. for information about internal clock states, see table 23 on page 54. for information about the maximum isa bus option, see page 65. parallel port interface ack printer acknowledge (input; active low) the printer asserts ack to confirm that the transfer from the lansc300 microcontroller to the parallel port was successful. afdt [x14out] auto line feed detect (output; active low) this pin signals the printer to autofeed continuous form paper. it can be programmed to become a 14.336-mhz output. busy printer busy (input; active high) the printer asserts busy when it is performing an operation. error (input; active low) the printer asserts the error signal to inform the parallel port of a deselect condition, pe, or other error condition. i nit [pcmcwe ] initialize printer (output; active low) this pin signals the printer to begin an initialization rou- tine. it can be programmed to become the pcmcia write enable signal (pcmcwe ). pe paper end (input; active high) the printer asserts this signal when it is out of paper. p pdwe [ppdcs ] parallel port write enable (output; active low) the ppdwe signal is used to control the 374 type latch in a unidirectional parallel port design. to support a bi- directional parallel port design, this pin can be reconfig- ured (ppdcs ) to act as an address decode for the parallel port data port. it can then be externally gated with ior and iow to provide the parallel port data read and write strobes, respectively. for more infor- mation, see parallel port on page 61. ppoen parallel port output buffer enable (output; active low) this signal supports a bidirectional parallel port design. it is used to control the output enable of the parallel port output buffer. slct printer select return (input; active high) the printer asserts slct when it has been selected. 38 lan?sc300 microcontroller data sheet preliminary slctin [pcmcoe ] printer selected (output; active low) asserting slctin selects the line printer. this pin can be programmed to become the pcmcia output enable signal (pcmcoe ). for more information, see parallel port on page 61. strb strobe (output; active low) asserting strb signals the line printer to latch data currently on the parallel port. serial port interface cts clear to send (input; active low) this signal indicates that the external serial device is ready to accept data. dcd data carrier detect (input; active low) this signal indicates to the internal serial port controller that the attached serial device has detected a data car- rier. dsr data set ready (input; active low) this signal is used to indicate that the external serial device is ready to establish a communication link with the internal serial port controller. dtr /cfg1 data terminal ready (output; active low) this signal indicates to the external serial device that the internal serial port controller is ready to communi- cate. the state of this signal is used to determine the pin configuration at power-up. for more information, see alternate pin functions on page 68. rin ring indicate (input; active low) this signal is used as a modem control function. a change in state on this signal by the external serial de- vice causes a modem status interrupt. this signal can be used to cause the lansc300 microcontroller to re- sume from a suspended state. rts /cfg0 request to send (output; active low) this signal indicates to the external serial device that the internal serial port controller is ready to send data. the state of this signal is used to determine the pin configuration at power-up. for more information, see alternate pin functions on page 68. sin serial data in (input; active high) this signal is used to receive the serial data from the external serial device into the internal serial port controller. sout serial data out (output; active high) this signal is used to transmit the serial data from the internal serial port controller to the external serial device. pcmcia interface bvd1_a (stschg_a ), bvd1_b (stschg_b ) battery voltage detect (inputs) these signals are generated by the memory card as an indication of the condition of its battery for a memory card interface. for an i/o card interface, these inputs are the cards status change interrupt (active low). bvd2_a (spkr_a ), bvd2_b (spkr_b ) battery voltage detect (inputs) these signals are generated by the memory card as an indication of the condition of its battery for a memory card interface. for an i/o card interface, these pins be- come the speaker inputs from the cards. ca24 card address bit 24 (output) this card address bit is controlled by accessing the lansc300 microcontroller configuration registers and should be connected to the card interface signal a24. this address signal is common to slot a and slot b in- terfaces. ca25 card address bit 25 (output) this card address bit is controlled by accessing the lansc300 microcontroller configuration registers, and should be connected to the card interface signal a25. this address signal is common to slot a and slot b in- terfaces. cd_a , cd_b card detect (inputs; active low) the card detect signals indicate that the card is prop- erly inserted into a socket. these signals should be driven from an anding of the cd1 and cd2 pins of a single socket. therefore, two external and gates are required, one for each slot. lan?sc300 microcontroller data sheet 39 preliminary icdir card data direction (output) this signal controls the direction of the card data buff- ers or translators, working in conjunction with the mcel_x and mceh_x card enable signals to control the data buffers on the card interface. when this signal is high, the data flow is from the lansc300 microcon- troller to the card socket, indicating a data write cycle. when this signal is low, the data flow is from the card socket into the lansc300 microcontroller, indicating a read cycle. note that pcmcia bus buffering may or may not be implemented in a system design. mceh_a , mceh_b card enables, high byte (output; active low) these signals enable odd address bytes for their re- spective card interfaces. mcel_a , mcel_b card enables, low byte (output; active low) these signals enable even address bytes for their re- spective card interfaces. pcmcoe card memory output enable (output, active low) the parallel port slctin signal can be programmed to become pcmcoe . pcmcoe indicates that a memory read cycle from the card interface is being performed. pcmcwe card memory write enable (output, active low) the parallel port init signal can be programmed to be- come pcmcwe . pcmcwe indicates that a memory write cycle to the card interface is being performed. rdy_a (ireq_a ), rdy_b (ireq_b ) card ready (inputs; active high) this signal indicates that the respective card is ready to accept a new data transfer command if a memory in- terface is selected. if the card interface is configured as an i/o interface, the socket a i/o cards ireq_a signal uses rdy_a as a general purpose input pin that may be used as the card interrupt request input into the lansc300 microcontroller (active high). for more in- formation about socket a cards ireq_a signal, see chapter 5 in the lan tm sc300 microcontroller pro- grammers reference manual , order #18470. reg_a , reg_b attribute memory select (output; active low) this signal selects either the attribute memory or the common memory. this signal will be inactive (high) for accesses to common memory, and asserted (low) for accesses to attribute memory. this signal is also as- serted (low) for all i/o accesses. rst_a, rst_b card reset (outputs; active high) these signals reset their respective cards. when ac- tive, this signal clears the card configuration option register, thus placing a card in a memory-only mode. vpp_a, vpp_b program and peripheral voltage control (output; active high) these signals can be used to enable the programming voltages to their respective card interfaces. wait_ab extend bus cycle (input; active low) this signal delays the completion of the memory ac- cess or i/o access that is currently in progress. when this signal is asserted (low), wait states will be inserted into the cycle in progress. a two-card solution needs each slots wait_ab signal anded before being input to the lansc300 microcontroller. wp_a (iois16a ), wp_b (iois16b ) write protect (inputs; active high) when a memory interface is selected, this signal indi- cates the status of the targeted devices write protect switch. when the targeted device is configured for an i/o interface, the wp_a signal is used to indicate that the currently accessed port is a 16-bit port (iois16 x ac- tive low). both wp_a and wp_b signals indicate that the tar- geted device is a 16-bit device during i/o access to the targeted device. when the targeted device is config- ured as an i/o access, the two signals are ord to- gether to generate the iois16 x signal. when the targeted device is configured as an i/o access, there is basically no difference between the wp_a and wp_b signals. 40 lan?sc300 microcontroller data sheet preliminary power management interface acin ac input status (input; active high) when asserted, this signal disables all power manage- ment functions (if so enabled). it can be used to indi- cate when the system is being supplied power from an ac source. bl4 Cbl1 battery low detects (inputs; negative edge sensitive) these signals are used to indicate to the lansc300 microcontroller the current status of the battery. bl4 C bl1 can indicate various conditions of the battery as status changes. a high indicates normal operating conditions, while a low indicates a low voltage warning condition. these inputs can be used to force the sys- tem into one of the power saving modes when acti- vated, as follows: n bl1 can be programmed to force the system to go to low speed pll mode or to generate an smi. n bl2 can be programmed to force the system to enter sleep mode if not already in sleep mode, or to generate an smi. n bl3 can only be programmed to generate an smi. n bl4 can be programmed to force the system to enter suspend mode. extsmi external system management interrupt (input; edge sensitive) this input is provided to allow external logic to gener- ate an smi request to the cpu. it is edge triggered, with the polarity programmable. lph latched power control (output; active low) this signal is the inverse of bl4 if acin is not true and bl4 is enabled. pgp3Cpgp0 programmable chip select generation (input/output) pgp0 and pgp1 can be programmed as input or out- put. the default is input. pgp2 and pgp3 are output only. these general purpose pins can be individually pro- grammed as decoder outputs or chip selects for other external peripheral devices. pgp0 and pgp2 can be gated with i/o write or act as an address decode only. pgp1 and pgp3 can be gated with i/o read or act as an address decode only. pgp0 and pgp1 can be directly controlled via a single register bit if configured to do so. pgp2 and pgp3 can also be configured for a specific state when the pmu is in the off state. pgp2 and pgp3 can be programmed to be set to a pre-defined state for micro power off mode. for more information about pgp3Cpgp0, see the lan tm sc300 microcontroller programmers refer- ence manual , order #18470b and using 10-bit romcs designs in lan tm sc300 and lansc310 mi- crocontrollers application note , order #21825. pmc4Cpmc0 power management controls (output; programmable) power management control outputs control the power to various external devices and system components. the pmc0, pmc1, pmc2, and pmc4 signals are as- serted low immediately after reset, and the pmc3 sig- nal is asserted high immediately after reset. each of the pmc pins can then be programmed to be high or low for each of the lansc300 microcontroller power management modes. sus / res suspend/resume operation (input; rising edge) when the lansc300 microcontroller is in high speed pll, low speed pll, or doze mode, a positive edge on this pin causes the internal logic to step down through the power management modes (one per re- fresh cycle) until sleep mode is entered. if in sleep, suspend, or off mode, a positive edge on this pin causes the lansc300 microcontroller to enter the high speed pll mode. display interface the signals listed as part of the display interface are only available when the lansc300 microcontroller is configured with the internal lcd controller enabled. if the internal lcd controller is disabled, the functions of these pins change to support either a cpu local bus in- terface or maximum isa bus interface. the pins re- quired for physical connection to the microcontroller are listed at the end of this section on page 42. for more information about the lcd controller, see the configuring the lan tm sc300 devices internal cga controller for a specific lcd panel application note , order #20749. lan?sc300 microcontroller data sheet 41 preliminary cp1 lcd panel line clock (output) this is the line clock when in internal lcd mode and an lcd configuration is selected. it is activated at the start of every pixel line refresh cycle. cp1 should be connected to the equivalent line on the lcd panel. cp2 lcd panel shift clock (output) this is the nibble/byte strobe when in internal lcd mode and an lcd configuration is selected. cp2 is also known as the shift clock or data shift. it is used by the lcd to latch data. cp2 should be connected to the equivalent line on the lcd panel. dsce display sram chip enable (output; active low) this signal generates the external video sram chip enable. dsma14Cdsma0 display sram address bus (output) these signals generate the address to the sram. up to 32 kbyte can be supported for the display interface. dsmd7Cdsmd0 display sram data bus (bidirectional) these signals provide the data bus used for the video sram. dsoe display sram output enable (output; active low) this signal controls the video sram output enable pin. dswe display sram write enable (output; active low) when asserted, this signal indicates a write to the video sram. frm lcd panel line frame start (output) this signal is asserted at the start of every frame (panel scan) when in lcd mode and an lcd configuration is selected. frm is also known as flm or frame. it should be connected to the equivalent line on the lcd panel. lcdd0 lcd data bit (output) when in internal lcd mode and an lcd configuration is selected, this signal is data bit 0. lcdd0 is the lsb and should be connected to the corresponding lsb pin on the lcd panel. lcdd1 lcd data bit (output) when in internal lcd mode and an lcd configuration is selected, this signal is data bit 1. lcdd1 should be connected to the corresponding pin on the lcd panel. lcdd2 lcd data bit (output) when in internal lcd mode and an lcd configuration is selected, this signal is data bit 2. lcdd2 should be connected to the corresponding pin on the lcd panel. lcdd3 lcd data bit (output) when in internal lcd mode and an lcd configuration is selected, this signal is data bit 3. lcdd3 is the msb and should be connected to the corresponding msb pin on the lcd panel. [lcddl3Clcddl0] lcd panel data bits for dual-scan panels (outputs) when the lansc300 microcontroller is programmed to support lcd dual-scan panel mode (separate data bits for the top and bottom half of the panel), these bits (lcddl3Clcddl0) are for the bottom half of the screen. lcdd3Clcdd0 are the data bits for the top half of the screen. lcd dual-scan panel mode is se- lected via firmware. lcddl0 is the lsb for the lower panel and lcddl3 is the msb for the lower panel. these pins are shared with iocs16 , mcs16 , irq14, and sbhe (described in system interface, beginning on page 35.) lcddl3Clcddl0 should be connected to their corresponding pins on the dual-screen lcd lower panel. lvdd lcd panel vdd voltage control (output; active low) this signal is used to control the assertion of the lcds vdd driver. lvdd is provided to be part of the solution in sequencing the panels vdd, data, and vee sig- nals in the proper order. lvee lcd panel vee voltage control (output; active low) this signal is used to control the assertion of the lcds vee driver. lvee is provided to be part of the solution in sequencing the panels vdd, data, and vee sig- nals in the proper order. 42 lan?sc300 microcontroller data sheet preliminary m lcd panel ac modulation (output) in internal lcd mode, this is the ac modulation signal for the lcd. ac modulation causes the lcd to change polarity on its crystal material to keep the lcd from forming a dc bias. some lcd panels do not require this signal. connect m to the equivalent line on the lcd panel if appropriate. lcd physical pin connections to connect an lcd panel to the lansc300 microcon- troller, the following pins need to be connected: n cp1 n cp2 n frm n lcdd3Clcdd0 n lcddl3Clcddl0 (dual-scan panel only) n m the other connections that are required vary. for ex- ample: n contrast voltage can be positive or negative, typi- cally about -22 v. n +5 v n gnd n display enable usually requires a simple 5-v enable signal that some panels require. this can easily be connected to one of the lansc300 microcontrol- lers pmc pins. n v ee is typically a voltage in the same range as the contrast voltage. refer to the panel specifications for more information. miscellaneous interface lf1, lf2, lf3, lf4 (analog inputs) loop filters these pins are used to connect external components that make up the loop filters for the internal plls. for more information, see loop filters on page 97. x1out [baud_out] 14-mhz/uart output this can be programmed to be either the 14.336-mhz clock or the serial baud rate clock for serial infrared de- vices. the 14.336-mhz output can be used by external video controllers. as baud_out, it is 16 x the bit data rate of the serial port and is used by serial infrared de- vices. [x14out] 14-mhz output the parallel port afdt output can be programmed to become x14out, a 14.336-mhz clock. x32in, x32out 32.768-khz crystal interface these pins are used for the 32.768-khz crystal. this is the main clock source for the lansc300 microcontrol- ler and is used to drive the internal phase-locked loops that generate all other clock frequencies needed in the system. for more information, see crystal spec- ifications on page 95. local bus interface the local bus interface pins are only available when the lansc300 microcontrollers internal lcd controller is disabled and the lansc300 microcontroller pin config- uration is set to support a cpu local bus and a partial isa bus. the following list of pins is specific to local bus function- ality. in local bus mode, additional isa pins are also available. these pins are described in the next section maximum isa bus interface because these pins are available in both local bus and maximum isa bus modes. for more information, see cpu local bus in- terface versus internal lcd interface on page 69 and tables 37C on page 73. a23Ca12 local bus upper address lines (output) these signals are the local bus cpu address lines when in local bus mode. these signals are combined with the sa11Csa0 signals to form the complete cpu address bus during local bus cycles. ads local bus address strobe (output; active low) local bus address strobe is an active low address strobe signal for 386 local bus devices. bhe local bus byte high enable (output; active low) this signal indicates to the local bus devices that data is being transferred on the high byte of the data bus. ble local bus byte low enable (output; active low) this signal indicates to the local bus devices that data is being transferred on the low byte of the data bus. lan?sc300 microcontroller data sheet 43 preliminary cpuclk cpu 2x clock (output) this is the timing reference for the local bus device. the high-speed pll can be programmed to provide one of the clock frequencies shown on page 53. cpurdy 386 cpu ready signal (output; active low) this signal shows the current state of the 386 core cpus cpurdy signal. cpurst cpu reset (output; active high) this signal is used to force the local bus device to an initial condition. it is also used to allow the local bus de- vice to synchronize to the cpuclk. this signal is taken directly from the internal cpu reset. d/c local bus data/control (output; active low) this signal indicates to the local bus devices that the current cycle is either a data cycle or a control cycle. a low on this signal indicates that the current cycle is a control cycle. ldev local bus device select (input; active low) this signal is used by the local bus devices to signal that they will respond to the current cycle. if ldev is not driven active by the time specified in table 57 on page 108, then the cycle defaults to an isa bus cycle. lrdy local bus device ready (input; active low) this signal is used by the local bus devices to terminate the current bus cycle. m/io local bus memory/i/o (output; active low) this signal indicates to the local bus devices that the current cycle is either a memory or an i/o cycle. a low on this signal indicates that the current cycle is an i/o cycle. w/r local bus write/read (output; active low) this signal indicates to the local bus devices that the current cycle is either a read or a write cycle. a low on this signal indicates that the current cycle is a read cycle. maximum isa bus interface the pins listed below as part of the isa bus interface are only available when the lansc300 microcontroller pin configuration is configured to enable the maximum isa bus. when the maximum isa bus interface is en- abled, the internal lcd controller and the cpu local bus interface are disabled. (this mode does not sup- port master and isa refresh cycles.) for more information, see maximum isa interface ver- sus internal lcd interface on page 70, table 37Ctable on page 73, and the lan tm sc300 and lan tm sc310 devices isa bus anomalies application note , order #20747. 0w s zero wait state (input; active low) this input can be driven active by an isa memory de- vice to indicate that it can accept a zero wait state memory cycle. bale bus address latch enable (output; active high) this pc/at-compatible signal is used by external de- vices to latch the la signals for the current cycle. dack7 , dack6 , dack5 , dack3 , dack2 , dack1 , dack0 dma acknowledge (output; active low) dma acknowledge signals are active low output pins that acknowledge their corresponding dma requests. note: the dack2 signal is available regardless of the lansc300 microcontrollers bus mode. dack1 and dack5 are also available in the local bus pin configu- ration. drq7, drq6, drq5, drq3, drq2, drq1, drq0 dma request (input; active high) dma request signals are asynchronous dma channel request inputs used by peripheral devices to gain ac- cess to a dma service. note: the drq2 signal is available regardless of the lansc300 microcontrollers bus mode. drq1 and drq5 are also available in the local bus pin configura- tion. iochchk i/o channel check (input; active low) this is a pc/at-compatible signal used to generate an nmi or smi. note: iochchk is also available in the local bus pin configuration. 44 lan?sc300 microcontroller data sheet preliminary irq15, irq14, i rq12Cirq9, irq7Cirq3, irq1 interrupt request (inputs; rising edge/active high trigger) interrupt request input pins signal the internal 8259 compatible interrupt controller that an i/o device needs servicing. irq3 and irq6 are shared with pirq0 and pirq1. irq0 is internally connected to the counter/timer, and irq8 is internally connected to the real-time clock. irq2 is used for cascading, and irq13 is reserved. irq0, irq2, irq8, and irq13 are not available exter- nally. note: irq4, irq12, and irq15 are also available in the local bus pin configuration. la23Cla17 latchable isa address bus (outputs) these are the isa latchable address signals. these signals are valid early in the bus cycle so that external peripherals may have time to decode the address and return certain control feedback signals such as mcs16 . lmeg address is in low meg (output; active low) this signal is active (low) whenever the address for the current cycle is in the first mbyte of memory ad- dress space (sa23 = sa22 = sa21 = sa20 = 0). note: lmeg should not be used to generate smemr or smemw . instead, address lines sa23Csa20 should be decoded. for more information about lmeg , see the lan tm sc300 and lan tm sc310 devices isa bus anomalies application note , order #20747. jtag boundary scan interface the lansc300 microcontroller provides an ieee std 1149.1-1990 (jtag) compliant standard test access port (tap) and boundary-scan architecture. the boundary-scan test logic consists of a boundary scan register and support logic that are accessed through the tap. the tap provides a simple serial in- terface that makes it possible to test the microcontroller and system hardware in a production environment. the tap contains extensions that allow a hardware- development system to control and observe the micro- controller without interposing hardware between the microcontroller and the system. the tap can be controlled via a bus master. the bus master can be either automatic test equipment or a component (pld) that interfaces to the four-pin test bus. the jtag pins described here are shared pin func- tions. they are enabled by the jtagen signal. jtagen jtag enable (input; active high) this pin enables the jtag pin functions. when it is high, the jtag interface is enabled. when it is low, the jtag pin functions are disabled and the pins are con- figured to their default functions. see the pin designa- tions, system interface, and miscellaneous interface tables for the jtag pin default function descriptions. for more information, see system test and debug on page 74. [tck] test clock (input) test clock is a jtag input clock that is used to access the test access port when jtagen is active. [tdi] test data input (input) test data input is the serial input stream for jtag scan input data when jtagen is active. [tdo] test data output (3-state output) test data output is the serial output stream for jtag scan result data when jtagen is active. [tms] test mode select (input) test mode select is an input for controlling the test ac- cess port when jtagen is active. reset and power see the voltage partitioning section on page 95 for more information about power. agnd analog ground pin this pin is the ground for the analog circuitry and is bro- ken out separately from the other gnd pins making it possible to filter agnd in a system that has a lot of noise on the ground plane. in most applications, agnd is tied directly to the ground plane with the other ground pins on the microcontroller. avcc 3.3 v (only) supply pin this supply pin provides power to the analog section of the lansc300 microcontrollers internal plls. ex- treme care should be taken that this supply voltage is isolated properly to provide a clean, noise-free voltage to the plls lan?sc300 microcontroller data sheet 45 preliminary avcc is required for battery backup. for more informa- tion about battery backup, see the lan tm sc300 and lan tm sc310 microcontrollers solution for systems using a back-up battery application note , order #20746. gnd system ground pins these pins provide electric grounding to all non-analog sections of the lansc300 microcontrollers internal cpu and peripherals. ioreset reset input (input; active low) ioreset is an asynchronous hardware reset input equivalent to powergood in the pc/at system ar- chitecture. asserting this signal does not reset the rtc ram invalid bit. asserting ioreset without asserting resin causes the lansc300 microcontroller to go into micro power off mode. for more information, see micro power off mode on page 55. resin master reset (input; active low) resin indicates that main power is being applied to the lansc300 microcontroller for the first time. when this signal is asserted, the rtc and internal registers are reset. the resin signal supersedes the ioreset signal. vcc 3.3 v (only) dc supply pins these supply pins provide power to the lansc300 mi- crocontroller core. refer to ac characteristics for vcc power up timing restrictions. the vcc pins are required for battery backup. for more information about battery backup, see the lan tm sc300 and lan tm sc310 microcontrollers solu- tion for systems using a back-up battery application note , order #20746. vcc1 3.3 v or 5 v supply pin this supply pin provides power to a subset of the lcd/ alternate, power management, and isa interface pins. vcc5 5 v dc supply pins these supply pins provide power to the 5 v only inter- face pins. these pins could be 3.3 v in a pure 3.3-v system. vmem 3.3-v or 5-v supply pins these supply pins provide power to the memory inter- face and data bus pins (d15Cd0). these pins must be connected to the same dc supply as the system drams. vsys 3.3 v or 5 v supply pins these supply pins provide power to a subset of the isa address and command signal pins, in addition to exter- nal memory chip selects, buffer direction controls, and other miscellaneous functions. vsys2 3.3 v or 5 v supply pins these supply pins provide power to some of the lansc300 microcontroller alternate system interface pins. functional description the lansc300 microcontroller architecture consists of several components, as shown in the device block diagram. these components can be grouped into eight main functional modules: 1. the am386sxlv microprocessor core itself, includ- ing system management mode (smm) power man- agement hardware 2. a memory controller and associated mapping hard- ware 3. two pcmcia revision 2.1 slots 4. an additional power management controller that in- terfaces to the cpus system management mode (smm) and is integrated tightly with internal clock generator hardware 5. core peripheral controllers (dma, interrupt control- ler, and timer) 6. additional peripheral controllers (uart, parallel port, and real-time clock) 7. pc/at support features 8. an integrated lcd controller, optional local bus controller, or optional maximum isa bus the remainder of this section describes these mod- ules. am386sxlv cpu core the cpu core component is a full implementation of the amd am386sxlv 32-bit, low-voltage microproces- sor (with i/o pads removed). for more information about the am386 microprocessors, see the 46 lan?sc300 microcontroller data sheet preliminary am386 a sx/sxl/sxlv data sheet , order #21020 and the am386 a dx/dxl data sheet , order #21017. along with standard 386 architectural features, the cpu core includes smm. smm and the other features of the cpu are described in the am386dxlv and am386sxlv microprocessors technical reference manual, order #16944. memory controller the lansc300 microcontroller memory controller is a unified control unit that supports a high-performance, 16-bit data path to dram or sram. no external mem- ory bus buffers are required and up to 16 mbyte in two 16-bit banks can be supported. system memory must always be configured as 16-bits wide. for more infor- mation about the memory controller, see chapter 2 of the lan tm sc300 microcontroller programmers refer- ence manual , order #18470. the system block dia- gram, figure 7 on page 64 of this manual, shows a typical palm-top memory configuration. the lansc300 microcontrollers memory controller supports an ems-compatible memory mapping sys- tem (mms) with 12 page registers. this facility can be used to provide access to rom-based software. mms is also used in the pcmcia slot support. shadow ram is also supported. the memory controller supports one of three different memory operating modes: sram, page mode dram, or enhanced page mode dram. enhanced page mode increases dram access performance by effec- tively doubling the dram page size in a two-bank dram system by arranging the address lines such that one page is spread across both dram banks. both dram modes use standard fast page mode drams. the memory controller operation is synchronous with respect to the cpu. this ensures maximum perfor- mance for all transfers to local memory. the clock stretching implemented by the clock generation cir- cuitry works to reduce synchronous logic power con- sumption. as shown in table 13, the two dram operating modes are defined by the mod field in the memory configura- tion register, index 66h, bit 0. the lansc300 microcontroller defaults to a dram in- terface. the sram mode is selected via bit 0 of the miscellaneous 6 register index 70h. the memory con- troller provides for a direct connection of two 16-bit banks supporting up to 16 mbyte of dram, utilizing in- dustry standard modules. the lansc300 microcon- troller shares the dram address lines ma0Cma11 with the upper system address lines sa12Csa23 to reduce pin count. this signal sharing is shown in table 14. the lansc300 microcontroller also shares the dram data bus with the system data bus on the d15Cd0 pins. in a typical system, an sd bus is created with an exter- nal x 16 bit buffer or level translator to isolate the dram data bus from the rest of the system. refer to the typical system block diagram, figure 7 on page 64 of this data sheet. the dram configurations are supported as shown in table 11. the bank size infor- mation in the table also applies when system memory is configured as sram; however, sram uses a differ- ent addressing scheme than dram and shares the same address lines as the isa bus. chapter 2 in the lan tm sc300 microcontroller programmers refer- ence manual , order #18470, contains more informa- tion. note that the configurations that use 512 kbyte x 8 bit and 1 mbyte x 16 bit drams employ asymmetrical addressing. table 16 and table 17 show the relation- ship of the cpu address mapped to the dram mem- ory. table 13. dram mode selection mod0 (index 66h, bit 0) function 0 page mode 1 enhanced page mode table 14. ma and sa signal pin sharing system address dram memory address sa23Csa14 ma9Cma0 sa13 ma10 sa12 ma11 lan?sc300 microcontroller data sheet 47 preliminary notes: 1. sram configuration is supported. bit 7 of the pcmcia card reset register, index b4h, must be cleared. setting ms2Cms0 of index 66h as specified in the table selects the sram bank sizes. see tables 16 and 17 for the dram address multiplexing schemes for normal page mode and enhanced page mode, respec- tively. table 15. supported dram/sram configuration bank size (16-bit wide only) index b1h index b4h index reg. 66h total dram/sram size bank 0 drams bank 1 drams bit 7 bit 6 bit 7 ms2 bit 4 ms1 bit 3 ms0 bit 2 512 kbyte 4 256 k x 4 bits 001xxx 512 kbyte 1 256k x 16 bits 0 0 1 x x x 1 mbyte 4 256 k x 4 bits 4 256 k x 4 bits 0 1 1 x x x 1 mbyte 1 256k x 16 bits 1 256k x 4 bits 0 1 1 x x x 1 mbyte 1 2 512 k x 8 bits xx0001 2 mbyte 1 2 512 k x 8 bits2 512 k x 8 bitsxx0010 2 mbyte 1 4 1 m byte x 4 bits xx0011 2 mbyte 1 1 m byte x 16 bits 101xxx 4 mbyte 1 4 1 m byte x 4 bits, 4 1 m byte x 4 bits xx0100 4 mbyte 1 1 m byte x 16 bits 1 1 m byte x 16 bits 111xxx 8 mbyte 1 4 4 m byte x 4 bits xx0101 16 mbyte 1 4 4 m byte x 4 bits 4 4 m byte x 4 bits xx0110 48 lan?sc300 microcontroller data sheet preliminary page mode dram using two banks of 1 mbyte x 16 drams is not supported. use enhanced page mode for two-bank configu- ration. see table 17 for the supported enhanced page mode configurations. see table 15 for the physical organization of the dram devices supported. bit 0 of the memory configuration 1 register, index 66h, must be cleared for normal (non-enhanced) page mode. notes: 1. asymmetrical addressing applies to configurations using dram with 512k x 8 and 1m x 16 organizations. table 16. dram address translation (page mode) index b4h index 66h index b1h dram dram address bit 7 bits 4 3 2 bits 7 6 size (byte) bank 0 (byte) bank 1 (byte) ras cas ma11ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 00 0 1 1 x x 1m 1m C ras cas C C C C a19 C a18 a9 a17 a8 a16 a7 a15 a6 a14 a5 a13 a4 a12 a3 a11 a2 a10 a1 0 0 1 0 1 x x2m1m1mras cas C C C C a19 C a18 a9 a17 a8 a16 a7 a15 a6 a14 a5 a13 a4 a12 a3 a11 a2 a10 a1 0 0 1 1 x x 2m 2m C ras cas C C C C a19 a10 a18 a9 a17 a8 a16 a7 a15 a6 a14 a5 a13 a4 a12 a3 a11 a2 a20 a1 01 0 0x x4m2m2mras cas C C C C a19 a10 a18 a9 a17 a8 a16 a7 a15 a6 a14 a5 a13 a4 a12 a3 a11 a2 a20 a1 0 1 0 1 x x 8m 8m C ras cas C C a22 a11 a19 a10 a18 a9 a17 a8 a16 a7 a15 a6 a14 a5 a13 a4 a12 a3 a21 a2 a20 a1 0 1 1 0 x x 16m 8m 8m ras cas C C a22 a11 a19 a10 a18 a9 a17 a8 a16 a7 a15 a6 a14 a5 a13 a4 a12 a3 a21 a2 a20 a1 1 x x x 0 0 512k 512k C ras cas C C C C C C a18 a9 a17 a8 a16 a7 a15 a6 a14 a5 a13 a4 a12 a3 a11 a2 a10 a1 1 x x x 0 1 1m 512k 512k ras cas C C C C C C a18 a9 a17 a8 a16 a7 a15 a6 a14 a5 a13 a4 a12 a3 a11 a2 a10 a1 1 x x x 1 1 0 2m 2m C ras cas a20 C a9 C a19 C a18 C a17 a8 a16 a7 a15 a6 a14 a5 a13 a4 a12 a3 a11 a2 a10 a1 lan?sc300 microcontroller data sheet 49 preliminary see table 11 for a description of the physical organization of the dram devices supported. bit 0 of the memory configuration 1 register, index 66h must be set to enable enhanced page mode. bit 1 of the memory con- figuration 1 register, index 66h, must be set for dram. if set for sram, bits 0 and 1 control wait states. sram notes: 1. bit 4 of the version register, index 64h must also be set for 2-mbyte enhanced page mode. also, bit 0 of memory configu- ration 1 register, index 66h, must be a 1. 2. when 16-mbit asymmetric drams are used in a two-bank configuration (4 mbyte), bits 1 and 0 of the memory configuration 1 register, index 66h, must be set for enhanced page mode only. when using sram instead of dram for main memory, up to 16 mbyte can be accessed, the sram being or- ganized as one or two banks. each bank is 16 bits wide and is provided with a low and high byte select. an sram memory interface is selected by setting bit 0 of the miscellaneous 6 register, index 70h. if this is done, cas1h , cas1l , cas0h , and cas0l will have their alternate function as sram chip select pins 3C0 (srcs3 Csrcs0 ). table 18 shows the key sram ac- cess pins. see table 15 on page 47 for bank size settings. the ms2Cms0 bits in the memory configuration reg- ister, index 66, are also used to program the total sram size. bit 7 of the pcmcia card reset register, index b4h, must be cleared for sram configurations. table 19 contains information about sram wait state logic, and table 30 on page 71 contains sram inter- face alternate pin information. table 17. dram address translation (enhanced page mode) index b4h index 66h index b1h dram dram address bit 7 bits 4 3 2 bits 7 6 size (byte) bank 0 (byte) bank 1 (byte) ras cas ma11ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 00 1 0 1 x x2m1m1mras cas C C C C a19 C a18 a9 a17 a8 a16 a7 a15 a6 a14 a5 a13 a4 a12 a3 a11 a2 a20 a1 0 1 0 0x x4m2m2mras cas C C C C a19 a10 a18 a9 a17 a8 a16 a7 a15 a6 a14 a5 a13 a4 a12 a3 a21 a2 a20 a1 0 1 1 0 x x 16m 8m 8m ras cas C C a22 a11 a19 a10 a18 a9 a17 a8 a16 a7 a15 a6 a14 a5 a13 a4 a23 a3 a21 a2 a20 a1 1 x x x 0 1 1m 512k 512k ras cas C C C C C C a18 a9 a17 a8 a16 a7 a15 a6 a14 a5 a13 a4 a12 a3 a11 a2 a19 a1 1x x x 2 1 14m2m2mras cas a 2 0 C a21 C a19 C a18 C a17 a8 a16 a7 a15 a6 a14 a5 a13 a4 a12 a3 a11 a2 a10 a1 table 18. sram access pins pin name i/o function srcs0 o sram bank 0 low byte select srcs1 o sram bank 0 high byte select srcs2 o sram bank 1 low byte select srcs3 o sram bank 1 high byte select sa23Csa1 o address (16 mbyte maximum) mwe o write enable 50 lan?sc300 microcontroller data sheet preliminary notes: refer to index 70h, bit 0, in the lan tm sc300 microcontroller programmers reference manual , order #18470 for information on how to select sram versus dram. pcmcia slots the lansc300 microcontroller supports two revision 2.1 pcmcia slots. mms mapping logic is used to access the pcmcia memory address space. up to twelve 16-kbyte pages of the cpus address space are mapped into windows of pcmcia memory address space. depending on the system requirements, the address and data lines to the pcmcia slots may or may not re- quire external buffers (see figure 7 on page 64). for more information, see chapter 2 in the lan tm sc300 microcontroller programmers reference manual , order #18470. also see the lan tm sc300 and lansc310 microcontrollers memory management ap- plication note , order #21823 and the using a pcmcia card as a boot rom on an lan tm sc300 microcon- troller design application note , order #21824. the pmu modes and clock generators the power management unit (pmu) monitors all sys- tem activities (e.g., keyboard, screen, and disk events), and, based on the state of the system, determines in which operating mode the system should be running. the pmu supports six operating modes, each defined by a different combination of cpu and peripheral oper- ation, as shown in the list that follows. 1. high-speed pll. all clocks are at their fastest speed and all peripherals are powered up. this is the mode the system enters when activity is de- tected by the pmu. 2. low-speed pll. the internal cpu clock is re- duced to a maximum of 4.608 mhz. all other clocks and peripherals operate at full speed. this is the first level of power conservation; it is entered after a specified elapsed time with no activity. 3. doze. the second level of power conservation. the cpu, system, and dma clocks are stopped. the high-speed pll is turned off. this mode is entered after a specified elapsed time with no activity. 4. sleep. additional clocks and peripherals are stopped after additional inactivity has been de- tected. the exact parameters can be programmed. the low-speed pll can be left on, so a quick star- tup is possible. 5. suspend. virtually all of the system is shut down, including all clocks, the 8254 timer, and the phase locked loops (a programmable recovery time is associated with this mode). the 32.768-khz clock input is still running. 6. off. this level is virtually the same as suspend mode. two outputs can be programmed to change state when the transition from suspend mode to off mode occurs. dram refresh can be disabled in off mode. in addition, the lansc300 microcontroller can man- age the power consumption of peripheral devices. this control can be forced upon entering a specific operat- ing mode or it can be handled directly by firmware. the lansc300 microcontroller pmu controls five power management control (pmc) pins that are controlled by the operating modes. clock generation the lansc300 microcontroller requires only one 32.768-khz clock input that is used to generate all other clock frequencies required by the system. this 32.768-khz clock input is provided through the x32in and x32out pins and the crystal oscillator circuit. this input frequency is then used to internally drive multiple phase-locked loops that create all necessary fre- quencies. the clock rate that is used to drive the internal cpu is determined by the mode of operation of the lansc300 microcontroller. the clock generation, control, and distribution scheme are detailed in figure 1 and figure 2, which follow. table 19. sram wait state select logic configuration number of wait states sram speed index 63h bit 4 index 66h bits 1 and 0 read write 20 mhz 25 mhz 33 mhz x 0 0 0 1 45ns 35ns 25ns 0 0 1 1 1 80ns 55ns 35ns 1 0 1 2 2 120 ns 100 ns 70 ns lan?sc300 microcontroller data sheet 51 preliminary int_pll ls_pll hs_pll vid_pll en 32 khz input ls_pll_en hs_pll_en vid_pll_en 1.4746 mhz 18.432 mhz 1.8432 mhz 1.1892 mhz 14.336 mhz en en en programmable 2 x cpu clock figure 1. pll block diagram ? 2 36.864 mhz 2.048 mhz 52 lan?sc300 microcontroller data sheet preliminary (isa cycle) + (dma cycle) + (low speed) 2 x cpu clock high speed pll (i 4 ) 18.432 mhz programmable low speed (i 0 Ci 3 ) divide chain 18.432 9.216 4.608 2.304 1.152 i 4 i 3 i 2 i 1 i 0 s 2 internal sysclk dma clock external sysclk 0 1 ? 2 ? 4 ? 2 2 x cpu/local bus clock s [1:0] figure 2. clock steering block diagram (low-speed pll mode only) lan?sc300 microcontroller data sheet 53 preliminary in the pll block diagram, the int_pll is the interme- diate pll, and is used to multiply the 32.768-khz input frequency by 45 to produce a 1.4746-mhz input for use by the ls_pll and the vid_pll. the ls_pll, or low- speed pll, is used to again multiply the 1.4746-mhz input by 25 to produce a 36.864-mhz output. this out- put of the ls_pll is then divided down to provide the frequencies shown in table 21. the ls_pll also generates a 2.048-mhz signal used by the vid_pll or video pll to generate the 14.336-mhz clock used by the internal lcd controller. this frequency is also available on the x1out pin for use by an external video controller if selected. the hs_pll can be programmed to provide one of the high-speed cpu clock frequencies shown in table 20. lansc300 microcontroller power management dynamic cpu clock switching is the primary form of power management in the lansc300 microcontroller. when the system is in the high-speed pll mode, the lansc300 microcontroller can be configured to use the high-speed clock output of the pll for main mem- ory, local bus accesses, cpu idle cycles, and rom ac- cesses configured to use the high-speed clock. during cycles to i/o devices, pcmcia, rom, and other exter- nal isa devices, the cpu clock is dynamically switched to the output of the low-speed pll. during operation in low-speed pll mode, the cpu clock is driven from low-speed clock output of the low-speed pll divide chain. the cpu clock fre- quency used during low speed mode is programma- ble to the following frequencies: 4.608 mhz, 2.304 mhz, 1.152 mhz, and 0.567 mhz. during doze, sleep, and suspend modes of operation, the cpu clock is normally stopped. this clock operates at 9.216 mhz when it is running. slow-refresh and self-refresh drams are supported by the lansc300 microcontroller. the refresh timer source and the refresh rate are selectable. when the cpu clock is stopped, the only clock source for refresh is the 32-khz clock. cas -before-r as dram refresh is performed. when the dma subsystem is idle, the dma clock con- trol logic stops the clock input to the dma controllers. the dma clock is started whenever any of the dreq inputs go high. when the dma cycle is in progress, the dma clock remains active as long as a dreq input is high or the internal aen signal is active. to reduce power consumption in doze, sleep, and suspend modes, the cpu clock is turned off. to further reduce the power consumption in these three modes, the high-speed pll is shut off. the low-speed pll is left on by default, but can be programmed to turn off in all three modes. for information about the signals associated with power management (acin, bl4 Cbl1 , extsmi, lph , pgp3Cpgp0, pmc4Cpmc0, and sus /res ), see power management interface on page 40. for more information, see chapter 1 of the lan tm sc300 micro- controller programmers reference manual , order #18470. table 20. high-speed cpu clock frequencies 2 x cpu frequency hs_pll output frequency 40 mhz 39.496 mhz 50 mhz 50.023 mhz 66 mhz 65.829 mhz table 21. pll output phase-locked loops frequency where used int_pll 1.4746 mhz ls_pll and vid_pll ls_pll 36.864 mhz divide by 2 1.8432 mhz 16450 uart clock 1.1892 mhz 8254 timer clock hs_pll 39.496 mhz, 50.023 mhz, or 65.829 mhz input to high speed/low speed mux vid_pll 14.336 mhz lcd controller 54 lan?sc300 microcontroller data sheet preliminary notes: all power management features will be disabled when ac power is detected via the acin pin being high. a register is provided to implement software acin by writing 1 to bit 5 in the miscellaneous 6 register, index 70h. the dma clock can be stopped except during dma transfers. the function enable register, index b0h, controls this function. the cpu clock speed in low-speed pll mode is selectable, (see the pmu control 3 register, index adh). the cpu clock speed: 1. can be programmed to run intermittently (on irq0) at 9.2 mhz. 2. programmable option (but not on per-clock basis; i.e., all clocks with this note are controlled by a single on/off select for that pmu mode). 3. programmable option, will reflect setting in suspend mode. 4. can be programmed to run at 9.2 mhz during temporary-on nmi/smi handlers. table 22. pmu modes mode description power on after power-on reset, system enters high-speed pll mode. high-speed pll the system will be in this mode as long as activities are detected by activity monitor (described in the pro- grammable activity mask registers, indexes 08h, 75h, and 76h). low-speed pll the system will enter this mode from high-speed pll mode after a programmable 1/512 s to 1/2 s, or 1/16 s to 16 s of inactivity. doze the system will enter this mode from low-speed pll mode after a programmable 1/16 s to 16 s, or 1/2 s to 128 s of inactivity. sleep the system will enter this mode from doze mode after a programmable 4 s to 17 minutes of inactivity. suspend the system will enter this mode from sleep mode after a programmable 1/16 s to 16 s of inactivity. off the system will enter this mode from suspend mode after a programmable 1 to 256 minutes of inactivity. table 23. internal clock states mode high-speed cpu clk low-speed cpu clk video clk dma clk sysclk 8254 clk (timer) 16450 clk (uart) high-speed pll 33/25/20 mhz 9.2 mhz 14.336 mhz 4.6 mhz 9.2 mhz 1.19 mhz 1.8432 mhz low-speed pll 4.608/2.304/ 1.152/0.567 mhz 4.608/2.304/ 1.152/0.567 mhz 14.336 mhz 2.3/1.2/ 0.58/0.29 mhz 9.2 mhz 1.19 mhz 1.8432 mhz doze dc 1 dc 1 14.3 mhz/dc 2 dc 1 9.2 mhz/dc 2 1.19 mhz/dc 2 1.8 mhz/dc 2 sleep dc 9.2 mhz/dc 4 14.3 mhz/dc 2 4.6 mhz/dc 4 dc 1.19 mhz/dc 2 1.8 mhz/dc 2 suspend dc 9.2 mhz/dc 4 14.3 mhz/dc 2 4.6 mhz/dc 4 dc 1.19 mhz/dc 2 1.8 mhz/dc 2 off dc 9.2 mhz/dc 4 14.3 mhz/dc 3 4.6 mhz/dc 4 dc 1.19 mhz/dc 3 1.8 mhz/dc 3 lan?sc300 microcontroller data sheet 55 preliminary pmc and pgp pins the lansc300 microcontroller supports five power management control (pmc) pins and four programma- ble general purpose (pgp) pins. the pmc pins can be used to control the vcc rails of peripheral devices. the pmc pins are related to the operating modes of the lansc300 microcontroller pmu. the pgp pins can be used as general i/o chip selects for various uses. the pmc4Cpmc0 pins are controlled by configuration registers at indexes 80h, 81h, abh, and ach. each pin can be programmed to be activated upon entry into any of the pmu modes or driven directly by software. pmc0 can be activated when the system is in high- speed pll or low-speed pll modes; pmc1 when the system is in doze mode; pmc2 when the system is in sleep mode; pmc3 and pmc4 when the system is in suspend mode; or just about any other combination. these pins can then be used by the system designer to shut off power to particular peripherals when the sys- tem enters certain modes, just as internal clocks are slowed or stopped in these modes. upon the rising edge of resin , pmc0, pmc1, pmc2, and pmc4 are asserted low and pmc3 is asserted high. prior to this edge, these signals are undefined. the lansc300 microcontroller can be programmed to reset a timer when an i/o access to a preset address range is detected. if no i/o activity in that range occurs before the timer expires, the lansc300 microcontrol- ler can assert a pmc signal to turn off the device. when s/w accesses that address range later, the lansc300 microprocessor can generate a system management interrupt (smi) to the processor, which then activates an smi handler routine. this routine then can deter- mine the cause of the smi and take appropriate action, such as powering the i/o device back on. the pgp3Cpgp0 pins are controlled by several config- uration registers (70h, 74h, 89h, 91h, 94h, 95h, 9ch, a3h, and a4h) and their behavior is very flexible. pgp0 and pgp1 can be programmed as input or output. pgp2 and pgp3 are dedicated outputs. pgp1 and pgp3 can be gated with i/o reads, pgp0 and pgp2 can be gated with i/o writes, or each can act as an ad- dress decode for a chip select. micro power off mode micro power off mode is the power management mode that is used for battery backup. micro power off mode allows the system designer to remove power from the vcc1, vsys, vsys2, vcc5, and optionally, vmem power inputs to the microcontrol- ler. this allows the rtc timer and ram contents to be kept valid by using a battery back-up power source on the vcc core and avcc pins, which typically should use only 25 m a in this mode. the following paragraphs describe the lansc300 mi- crocontroller in micro power off mode. the following are distinctive characteristics: n minimum power consumption mode (approxi- mately 25 m a typical, avcc, and core vcc com- bined; avcc and vcc are mandatory for micro power off mode). n allows the system designer to utilize the internal rtc and rtc ram to maintain time, date, and system configuration data while the other system peripherals are powered off. n provides the system designer with the option of keeping the system dram powered and refreshed while other system peripherals are powered off. self-refresh and cas -before-ras refresh drams are supported. n minimal external logic required to properly control power supplies and/or power switching. n no external buffering required to properly power down system hardware. the lansc300 microcontroller allows a system de- signer to easily maintain the internal rtc and rtc ram and optionally, the dram interface, while the rest of the system peripherals attached directly to the de- vice are powered off. all lansc300 microcontroller power pins associated with the i/o pins of external powered-off peripherals must be powered down also. this, in addition to internal termination, provides the re- quired isolation to allow the external peripherals to be powered off. automatically controlled internal i/o termination is pro- vided to terminate the internal nodes of the lansc300 microcontroller properly when required. the dram cas -before-ras , or self-refresh, can be maintained by the lansc300 microcontroller in this micro power state, if configured to do so, utilizing the 32-khz oscillator. this clock continues to drive the rtc and a portion of the core logic. see the lan tm sc300 and lan tm sc310 microcontrollers solution for sys- tems using a back-up battery application note , order #20746 for more information about the 32-khz oscilla- tor and the rtc. the vmem power plane (dram/ sram section power) must remain powered on if the cas -before-ras refresh option is selected while in the micro power state. the vmem power plane must also remain powered on if the self-refresh option is selected and the specific dram device requires any of its con- trol pins (i.e., we , cas , ras , etc.) to remain inactive in the self-refresh mode. if this is not required, it may be possible for the system designer to remove power from the vmem pins when entering the micro power state, even when the self-refresh mode drams remain powered on. 56 lan?sc300 microcontroller data sheet preliminary a portion of a typical system using a secondary power supply to maintain the rtc and rtc ram (and option- ally system dram) is shown in figure 3. this second- ary power supply could be as simple as a small lithium coin cell battery as indicated in the diagram, but is cer- tainly not limited to this. note that when all primary power supply outputs are turned off, all of the systems peripherals are powered off (dram optional), all of the lansc300 microcontrollers power planes are pow- ered off except avcc (analog) and vcc (core), and the secondary power supply is switched in to maintain the lansc300 microcontrollers core and analog power source. for more information about back-up batteries, see the lan tm sc300 and lan tm sc310 microcontrollers solu- tion for systems using a back-up battery application note , order #20746. the resin pin acts as the master reset. when active, all of the internal registers and components are reset, including the rtc, and the rtc ram invalid bit will be set. this causes an issue with the power-loss bit (vrt), index 0dh, bit 7 of the rtc map. the vrt bit is in- tended to provide a method of determining when the rtc core voltage supply has dropped below an ac- ceptable level. on a 146818a-compatible device, anything below 2.4 v will cause a low-battery condition and will cause the power-loss bit to go low. on the lansc300 micro- controller, the 32-khz clock used by rtc to maintain time stops oscillating before the vrt bit or ram con- tents get cleared because the vrt bit will only get cleared when the resin pin is asserted low. thus, the rtc time will be inaccurate even though the ram con- tents are valid and the vrt bit is still set. note: although the 32-khz clock stops oscillating be- fore the power-loss bit is cleared, this event occurs well before the 2.4-v specification for proper lansc300 microcontroller functionality. the resin pin should only be asserted (pulsed) low when a power source is initially applied to the devices core and analog sections. for more information about these notes, see the lan tm sc300 and lan tm sc310 microcontrollers solu- tion for systems using a back-up battery application note , order #20746. the ioreset signal is intended to be the normal power good status from the primary power supply in the example design shown in figure 3. the iore- set input does not reset the rtc and will not set the rtc ram invalid bit. ioreset (when the inactive state is detected) will cause the lansc300 microcontroller to go through its power-up sequence including pll start-up for clock generation and an internal cpu reset. see figure 32 through figure 35, beginning page 100, for the initial power-up timing requirements and for micro power mode exit timing. on/off acin lansc300 microcontroller rtc pmu power supply swapping circuit primary power supply secondary power supply ioreset m e m o r y p c m c i a l o c a l / l c d main battery + - 3.3 v 5 v parallel/serial power management analog isa/local/lcd isa/ isa and misc. resin r c vcc (core) avcc figure 3. typical system design with secondary power supply to maintain rtc when primary power supply is off (dram refresh is optional.) lan?sc300 microcontroller data sheet 57 preliminary when entering micro power off mode and the primary power supply outputs are turned off, all of the lansc300 microcontrollers powered-down i/o pins are essentially tri-stated and the internal pull-ups are removed because the vccio and vcc clamp of the output driver have been removed, as shown in figure 34 on page 101. this provides the ability to power off external peripherals that are attached directly to the lansc300 microcontroller without concern of driving current into the pins of the external powered-down de- vice. to assure that the lansc300 microcontroller does not draw excessive power while in this state, internal pull- down resistors will be enabled. enabling these resis- tors keeps the input buffers from floating (see figure 4). the lansc300 microcontroller samples the two reset inputs (resin and ioreset ) to logically determine what state the power pins are in; and, in turn, controls the internal pull-down resistors. note that in micro power off mode, the ioreset input should be termi- nated with a pull-down resistor if not driven low by an external device (see table 24 on page 59 for informa- tion about internal i/o pull-down states). micro power off dram refresh refresh can be either enabled or disabled during micro power off mode, and the vmem power can be option- ally removed, provided that either the memory is also powered off or all dram interface signals are kept at 0 v. see the timing diagrams in figure 34 and figure 35 on page 101 for more information. the system designer has the option to keep the system dram powered up and refreshed while the lansc300 microcontroller is in the micro power state. a configura- tion bit, the micro power refresh enabled bit, exists in the pmu section of the core logic to realize this feature. this is bit 2 of the miscellaneous 3 register at index bah. if this bit is cleared (default), the core logic asso- ciated with the dram refresh will be disabled when the lansc300 microcontroller is in the micro power state. if the bit is set, the core logic associated with the dram refresh will be enabled and functional while the lansc300 microcontroller is in its micro power state. in buf level translator and pre-driver level translator and pre-driver i/o pad pull-up resistor vccio vcc clamp core logic i/o driver pins to core logic vcc core force term pull-down resistor data out output enable where: vccio = vcc5, vmem, vsys, vsys2, avcc, or vcc1 vcc clamp = vcc5, vmem, or avcc figure 4. lansc300 microcontroller i/o structure 58 lan?sc300 microcontroller data sheet preliminary the type of micro power dram refresh performed (cas -before-ras refresh, or self refresh) will be the same as that for which the part was configured before the ioreset pin sampled low. if the micro power re- fresh feature is enabled for cas -before-ras refresh, the system designer should maintain power on the vmem power pin of the lansc300 microcontroller and not remove power from the dram devices. if the micro power refresh feature is enabled for self refresh, the system designer may or may not be required to maintain power on the vmem power pin of the lansc300 microcontroller, depending on the specific requirement of the dram device in self-refresh mode. power should not be removed from the dram device itself in either case. the micro power refresh bit will always be cleared whenever the resin input is sampled low. therefore, when the core is initially powered up, the micro power dram refresh feature will be disabled. this bit is unaf- fected by the ioreset input. this bit will provide the system bios with a mechanism to determine whether or not the system dram data has been retained after a reset (ioreset ) has occurred. if self-refresh mode is selected and enabled for micro power off mode, then when micro power off mode is exited, the lansc300 microcontroller will properly force a cas -before-ras refresh cycle to cause the drams to exit the self-refresh mode. the lansc300 microcontroller then transitions to the normal cas -be- fore-ras refresh mode. this functionality is exactly the same as the self-refresh mode exit when the cpu clock stopped mode is exited. the lansc300 micro- controller generates one cas -before-ras refresh cycle to force the dram to exit the self-refresh mode. this is also true for the micro power dram refresh fea- ture. the timing diagrams in figure 34 and figure 35, on page 101, show the sequence required to guarantee a proper transition into the micro power state. this se- quence is especially critical when the dram refresh option is selected. note that the power pins of the lansc300 microcontroller must be kept stable for some time after the ioreset input has gone active. stable means that these power pins should remain at least at their vcc (min) value for the specified time in- dicated in table 51 on page 99. r esin and ioreset the lansc300 microcontroller has two reset inputs to support the micro power off mode. these two inputs are resin and ioreset . if micro power off mode is not to be used, the system designer should drive these two inputs from a common power-on reset source. note that the resin signal is a 3.3-v only input and is not 5-v safe. for more information, see table 24 on page 59. rstdrv signal timing rstdrv is high true output of the lansc300 micro- controller and is a function of the internal cores reset state, the state of the resin and ioreset signals, and the value for the pll start-up timer in the clock control register (index 8fh). (see loop filters on page 97 for more information.) rstdrv indicates that the plls are gated off from the core and prevents the cpu from executing instructions until the pll outputs have stabi- lized. rstdrv is asserted immediately whenever vcc power is applied and either resin or ioreset is as- serted. the pulse width of rstdrv may vary and is determined by the pll start-up timer and whether or not ioreset and/or resin is deasserted (i.e., cold boot versus warm reset or micro power off mode exit). on a cold boot, when resin is asserted while power is applied to the vcc inputs and then deasserted after time delay (t1), the rstdrv is immediately asserted when power is applied, and then held true until resin and ioreset are deasserted. because the assertion of resin causes all the configuration registers to be reset to their default values, the pll start-up time value in the clock control register is set to 4 ms and is insuffi- cient time for the plls to start up. this is why the vcc- to-resin timing specification (t1) of 1 second is re- quired to allow sufficient time for the crystal and the plls to power up and stabilize before resin and iore- set allow rstdrv to be deasserted. on a warm reset, the power stays on and the vcc in- puts are already powered up while the plls are either powered and running or gated off. rstdrv is asserted quickly after resin is asserted, with the pulse width also determined by the resin pulse width, because the default pll start-up timer has a value of 4 ms. it is therefore recommended that the system design guar- antees at least a minimum resin pulse width of 250 ms for warm resets. on a wake-up from micro power off mode, vcc and avcc power to the core is maintained active, and the clock configuration register value for the pll start-up timer is preserved, but power is removed from all the other vcc inputs, and the plls are gated off. rstdrv is asserted internally, and the output is driven active as soon as vsys is powered up. when ioreset is first asserted to go into micro power off mode, rstdrv is immediately asserted high. when power is removed from the vsys input (which is also vccio for rst- drv), the voltage level of rstdrv begins to decay at the same rate as vsys until it reaches approximately 0.7 v, where it remains while in micro power off mode. this indicates that rstdrv is still asserted internally inside the microcontroller and is attempting to drive the external pin high, but is unable to without power ap- plied to its i/o driver. when exiting micro power off lan?sc300 microcontroller data sheet 59 preliminary mode, as soon as vsys is powered up, rstdrv is im- mediately driven high and will remain high until the ioreset signal is deasserted and the preserved pro- grammed value in the pll start-up timer has expired. force term figure 4 on page 57 shows the schematic diagram, and table 24 shows the function of the ioreset , resin, and force term. when in micro power off mode, it is important not to back power any of the pow- ered-off internal power planes. table 2 Ctable 11 show the vccio and vcc clamp voltage sources for each signal pin. ensure that all signals, which are either driven by (vccio) or clamped to (vcc clamp) a pow- ered-off voltage source, are also either powered off or driven low. pgp pins pgp2 and pgp3 can be programmed to be set to a pre-defined state for micro power off mode. for more information, see the lan tm sc300 microcontroller pro- grammers reference manual , order # 18470. micro power off mode implementation the system should not be powered up directly into micro power off mode. the system must be allowed to fully power up into high speed mode upon initial power application of any power source. if a battery has insuf- ficient power for the lansc300 microcontroller to ini- tialize into high speed mode, the system design must first power up the lansc300 microcontroller from the main source, and not allow the chip to be powered from the battery until after it is fully initialized in high speed mode and properly transitioned into micro power off mode. this requirement presents an issue when using (for ex- ample) a 3-v lithium battery cell as a back-up power source to prevent the rtc from losing its contents dur- ing micro power off mode. if the battery is installed be- fore any other power source is available, the requirement cannot be met because such a small bat- tery is incapable of supplying sufficient power to fully initialize the system. the lansc300 microcontroller comes up in an undefined state, perhaps drawing suf- ficient current to drain the battery. the lansc300 microcontroller backup power source should be installed only after the system is powered by the main power source prior to a transition into micro power off mode. when the system has transitioned into micro power off mode properly, the simultaneous benefits of low power consumption while maintaining rtc data such as time, date, and system configuration can be realized. note: the timing sequence and specifications for power-up, entering, and exiting micro power off mode must be met. the timing specifications are shown in table 51 on page 99. for more information, see the lan tm sc300 and lan tm sc310 microcontrollers solution for systems using a back-up battery application note , order #20746 and the troubleshooting guide for micro power off mode on lan tm sc300 and lansc310 mi- crocontrollers and evaluation boards application note , order #21810. table 24. internal i/o pulldown states ioreset resin force term comments 0 0 active this condition occurs when any power source is initially turned on. the lansc300 microcontrollers core and analog vcc is transitioning to on and resin is active (the initial power-up state). see the micro pow- er off mode implementation section below for more details. 0 1 active this condition occurs when the core and analog vcc is stable, the resin pin has been inactive, and the primary power supply outputs are off (the normal micro power off state). 1 0 active this condition should be treated as condition 0,0 above. 1 1 inactive this occurs when the secondary power supply is on, the resin input is inactive, and the primary power supply is on and has deassert- ed ioreset (normal system operating state). 60 lan?sc300 microcontroller data sheet preliminary core peripheral controllers the lansc300 microcontroller includes all the stan- dard peripheral controllers that make up a pc/at sys- tem, including interrupt controller, dma controller, counter/timer, and isa bus controller. for more infor- mation, see chapter 4 of the lan tm sc300 microcon- troller programmers reference manual , order #18470. interrupt controller the lansc300 microcontroller interrupt controller is functionally compatible with the standard cascaded 8259a controller pair as implemented in the pc/at. the interrupt controller block accepts requests from peripherals, resolves priority on pending interrupts and interrupts in service, issues an interrupt request to the processor, and provides the interrupt vector to the processor. the two devices are internally connected and must be programmed to operate in cascade mode for operation of all 15 interrupt channels. interrupt controller 1 occu- pies i/o addresses 020hC021h and is configured for master operation in cascade mode. interrupt controller 2 occupies i/o addresses 0a0hC0a1h and is config- ured for slave operation. channel 2 (irq2) of interrupt controller 1 is used for cascading and is not available externally. the output of timer 0 in the counter/timer section is connected to channel 0 (irq0) of interrupt controller 1. irq0 can be programmed to generate an smi. see chapter 1 of the lan tm sc300 microcontroller pro- grammers reference manual , order #18470. interrupt request from the real-time clock is connected to channel 0 (irq8) of interrupt controller 2. irq13 is re- served for the coprocessor in a pc/at system and is unavailable on the lansc300 microcontroller. the other interrupts are available to external peripherals as in the pc/at architecture via the irq15, irq14, irq12Cirq9, irq7Cirq3, and irq1 inputs. other sources of interrupts are smi/nmi and the pirq1C pirq0 inputs. the lansc300 microcontroller interrupt controller has programmable sources for interrupts. these program- mable sources are controlled by the configuration reg- isters. for more information, see chapter 5 of the lan tm sc300 microcontroller programmers refer- ence manual , order #18470. the interrupt controller provides interrupt information to the lansc300 microcontroller power management unit to allow the monitoring of system activity. the lansc300 microcontroller power management unit can then use the interrupt activity to control the power management mode of the lansc300 microcontroller. for more information, see chapter 1 of the lan tm sc300 microcontroller programmers refer- ence manual , order #18470. dma controller the lansc300 microcontroller dma controller is func- tionally compatible with the standard cascaded 8237 controller pair. channels 0, 1, 2, and 3 are externally available 8 bit channels. dma channel 4 is the cas- cade channel. channels 5, 6, and 7 are externally available as 16 bit channels. all the dma channels are masked off on hardware reset or when writing the dma master reset register. note: to enable the master to percolate the request to the cpu, you must also unmask the cascade channel (0) on the master. the lansc300 microcontroller supports the power- saving clock stop feature that causes the clock to the dma controller to stop except when actually needed to perform a dma transfer. for more information about clock states and programmable clock frequencies, see table 23 on page 54. the lansc300 microcontroller supports single, block, and demand transfer modes; however, soft- ware-initiated dma requests, cascade mode for addi- tional external dma controllers, and verify mode are not supported. for more information about the dma controller, see the lan tm sc300 microcontroller programmers refer- ence manual , order #18470. counter/timer the lansc300 microcontrollers counter/timer is func- tionally compatible with the 8254 device. a 3-channel, general-purpose, 8254 compatible, 16-bit counter/ timer is integrated into the lansc300 microcontroller. it can be programmed to count in binary or in binary coded decimal (bcd). each counter operates inde- pendently of the other two and can be programmed for operation as a timer or a counter. all three are con- trolled from a common set of control logic, which pro- vides controls to load, read, configure, and control each counter. all of the 8254 compatible counter/timer channels are driven from a common clock that is internally generated from the ls_pll 1.1892-mhz output. the output of counter 0 is connected to irq0. additional peripheral controllers the lansc300 microcontroller also integrates three other peripheral controllers commonly found in pcs, but not considered part of the core peripherals, namely a serial port or a universal asynchronous re- ceiver transmitter (uart), a real-time clock (rtc), lan?sc300 microcontroller data sheet 61 preliminary and a parallel port. see chapter 4 of the lan tm sc300 microcontroller programmers reference manual , order #18470. 16450 uart the lansc300 microcontroller chip includes a uart, providing lansc300 microcontroller systems with a serial port. this serial controller is fully compatible with the industry-standard 16450. in handheld systems, this port can connect to the pen input device or to a modem. real-time clock the lansc300 microcontroller contains a fully 146818a-compatible real-time clock (rtc) imple- mented in a pc/at-compatible fashion. the rtc drives its interrupt to power-management logic. the rtc block in the lansc300 microcontroller con- sists of a time-of-day clock with alarm and 100-year calendar. the clock/calendar can be represented in bi- nary or bcd. it has a programmable periodic interrupt, and 114 bytes of general purpose static ram (an ex- tension of the 146818a standard, see the program- mers reference manual for more details). parallel port the lansc300 microcontroller parallel port is func- tionally compatible with the ps/2 parallel port. the lansc300 microcontroller parallel port interface pro- vides the parallel port control outputs and status inputs, and also the control signals for the parallel port data buffers. the parallel port data path is external to the lansc300 microcontroller. this interface can be con- figured to operate in either a unidirectional (normal) mode or bidirectional (epp) mode. the unidirectional parallel port requires only one exter- nal component, the parallel port data latch. this latch is used to latch the data from the data bus and drive the data onto the parallel port data bus, as shown in figure 5. when the lansc300 microcontroller parallel port is configured for bidirectional mode operation, the ppdwe pin is reconfigured via firmware to function as the parallel port data register address decode (ppdcs ). the ppoen output from the lansc300 mi- crocontroller is controlled via the parallel port control register bit 5. this signal is then used to control the output enable of the external parallel port data latch. by setting this bit, the parallel port data latch is disabled, and then data can be transferred from an external par- allel port device into the lansc300 microcontroller through an external 244 type buffer. a typical bidirec- tional parallel port data bus implementation is shown in figure 6. if the vcc5 supply pins are connected to a 5-v power supply, then the parallel port control signals will be driven by 5-v outputs and can be connected directly to the parallel port connector. if vcc5 is connected to 3.3 v, the parallel port control signals should be translated to 5 v. the lansc300 cpu also supports enhanced parallel port (epp) mode. the epp mode pins are defined in table 25. note: if pcmcia write enable ( pcmcwe ) and pcm- cia output enable ( pcmcoe ) are used, the parallel port signals init and slctin are not available. in normal mode, the outputs shown in table 25 func- tion as open-collector or open-drain outputs. in epp mode, these outputs must function as standard cmos outputs that are driven high and low. figure 6 shows the design that should be used to support epp mode. figure 5. lansc300 microcontroller unidirectional parallel port data bus implementation 374 octal d flip flop sd7Csd0 ppdwe parallel port data bus clk oe dq table 25. parallel port epp mode pin definition normal mode epp mode description strb write epp write signal. this signal is driven active during writes to the epp data or address regis- ter. afdt dstrb epp data strobe. this signal is driven active during reads or writes to the epp data register. slctin astrb epp address strobe. this sig- nal is driven active during reads or writes to the epp ad- dress register. ack intr epp interrupt. this signal is an input used by the epp device to request service. busy wait epp wait. this signal is used to add wait states to the current cycle. it is similar to the isa iochrdy signal. 62 lan?sc300 microcontroller data sheet preliminary parallel port anomalies general the lansc300 microcontroller parallel port can be physically mapped to three different i/o locations or can be completely disabled. these i/o locations are 3b(x)h, 37(x)h, and 27(x)h. typically the system bios or a software driver sets up the port at system boot time. generally, lpt1 is set up by software to be asso- ciated with irq7, and lpt2 (and lpt3 if desired) is set up to be associated with irq5. in the lansc300 mi- crocontroller, the parallel port is always associated with irq7. this cannot be changed regardless of the i/o location to which the parallel port is mapped. local bus or maximum isa configuration when the lansc300 microcontroller is configured for some bus mode other than the internal cga controller option, the system bios should disable the internal video controller at boot time. this is done by setting bit 5 of the screen control register 2, index 19h in the cga index address space. control register 1, index 20h in the cga index ad- dress space, controls the parallel port mapping. when the internal cga controller is disabled, control regis- ter 1 cannot be accessed until the part is reset. there- fore, once the internal cga controller has been disabled, the parallel port cannot be remapped. this can cause the system boot sequence to require modi- fication such that the parallel port is set up prior to the disabling of the internal video controller. in addition, any software driver or setup utility which was loaded after the internal video controller was disabled would not have the ability to remap the parallel port location if it was required. for more information about parallel ports, see chapter 4 of the lan tm sc300 microcontrol- ler programmers reference manual , order #18470. pc/at support features the lansc300 microcontroller provides all of the sup- port functions found in the original pc/at. these in- clude the port b status and control bits, speaker control, extensions for fast reset, and a20 gate control. (fast cpu reset and fast a20 gate functions are con- trolled by either the miscellaneous 1 register, index 6fh, or port 92h). for more information, see chapter 4 of the lan tm sc300 microcontroller programmers reference manual , order #18470. the lansc300 microcontroller also includes support for port b, and a miscellaneous pc/at register that al- lows direct programming of the speaker via the spk line. in addition, the lansc300 microcontroller also generates a chip select and clock source for an exter- nal, standard 8042 keyboard controller or the pc/xt keyboard feature. for more information, see appendix b of the lan tm sc300 microcontroller programmers reference manual , order #18470. port b and nmi control port b is a pc/at-standard miscellaneous feature con- trol register that is located at i/o address 061h. the 373 octal d transparent latch sd7Csd0 parallel port data bus dq en oe ppoen iow ior 244 type buffer ya enb ppdcs figure 6. the lansc300 cpu bidirectional parallel port and epp implementation lan?sc300 microcontroller data sheet 63 preliminary lower 4 bits of the 8-bit register are read/write control bits that enable or disable nmi check condition sources and sound generation features. the top, or most signif- icant, 4 bits are read/write bits that return status and di- agnostic information and control the pc/xt keyboard interface. there is a master nmi enable function provided that can inhibit any nmis from reaching the cpu regardless of the state of the individual source enables. this mas- ter nmi control is located as a single bit (7) of the reg- ister at i/o address 070h. the default value for the nmi enable bit is 1, which inhibits nmi generation.the nmi enable bit (7) is a write-only bit, and is active low. the remaining bits of the register located at 070h ( 6C0) con- trol the rtc function. because the rtc portion of this register is only 7 bits wide and is also write only, there is no conflict between the two functions. this register is discussed in more detail in the rtc section of chapter 4 of the lansc300 microcontroller programmers ref- erence manual , order #18470. speaker interface the pc/at standard tone generation interface for the system speaker is implemented in the lansc300 mi- crocontroller. there are two data paths to the spkr pin of the device. the first path is driven by the output channel 2 of the internal 82c54 counter/timer. the counter/timer can be programmed in various ways to generate a waveform at the output, out2. also, the gate input of timer channel 2 is controlled by the t2g bit in port b. the timer gate can be used to inhibit tone generation by the timer channel. the second path is driven directly by the spk bit in port b. this bit can be manipulated by the cpu to generate almost any digital waveform at the spkr pin. fast a20 address control with the lansc300 microcontroller, full real mode ad- dress compatibility requires that address rollover at the 1-mbyte address boundary be handled the same way as the early 8088-based pcs were handled. this re- quires the system address line 20 to have the capability of being forced to 0 during real mode execution. con- trol of the a20 line is supported from multiple sources. the a20g signal in pc/at systems is normally con- nected to an output of the pc/at keyboard controller. a logic high on this input forces the pass through of the cpus a20 onto the internal system address bus. a logic low on this input forces the system address bus a20 line low, as long as the internal a20 gate control is not being utilized. the lansc300 microcontroller provides a high-perfor- mance method for controlling the system a20 line, in- dependent of the relatively slow pc/at keyboard controller. this internal a20 gate control is generated by the miscellaneous 1 register, index 6fh, and port 92h. for more information, see the lan tm sc300 and lansc310 microcontrollers gatea20 function clari- fication application note , order #21811. reset control an external hardware reset is required in order to cor- rectly initialize internal logic after system power-up. see the required timings in table 51 on page 99. sys- tem power supplies typically have a powergood output signal that is used as an active low asynchro- nous reset input for the device. ioreset is intended to be driven by a powergood-compatible signal. when ioreset is driven lo w, the lansc300 micro- controller resets all of its internal logic with the excep- tion of the rtc valid data/time bit (register d, rtc index 0dh, bit 7) and some internal register configura- tion bits. the resin input is intended to be driven by a signal that indicates that the battery back-up source has been disconnected. when resin is driven low, the lansc300 microcontroller resets all of its internal logic. the resin input buffer is a schmitt trigger for tol- erance of slow rise and fall times on the signal. resin and ioreset are internally synchronized to the cpu clock to provide the internal hardware reset. for more information, see table 24 on page 59 and micro power off mode on page 55. besides the device hardware reset, the internal cpu has several other possible reset sources. these other sources only generate cpu reset. in a standard pc/at-type system, an rc (cpu reset) pin is typically connected to an output of the 8042 key- board controller. also, an internal configuration register can be used to reset the cpu in less time than that required by the ex- ternal keyboard controller. the internal reset is con- trolled by the miscellaneous 1 register, index 6fh, and port 92h. the lansc300 microcontroller provides both of the cpu reset functions described above and also triggers a cpu reset upon processor shutdown. if the cpu reaches a state where it cannot continue to execute be- cause of faults and error conditions, it will issue a status code indicating shutdown, and the cpu will halt opera- tion with no means of continuing except for a reset. if this shutdown status is detected, a 16 clock minimum pulse width reset is automatically sent to the cpu. 64 lan?sc300 microcontroller data sheet preliminary dsmd7Cdmsd0 ma10Cma0 d15Cd8 ma10Cma0 d7Cd0 b u f max241 video sram lcd lan sc300 microcontroller 512k x 8 512k x 8 1 mbyte system memory 3.3 v or 5 v pcmcia pcmcia rom/flash bios rom/flash dos keyboard controller (8042) l a t c h parallel port control dsma14Cdmsa0 b u f ma10Cma0 d15Cd0 slot a control slot b control sa12Csa0 sa23Csa13 sd15Csd0 b u b u f b u f b u f b u f ras cas we serial port * * note: *optional miscellaneous i/o control * * figure 7. typical system block diagram (internal lcd controller) lan?sc300 microcontroller data sheet 65 preliminary lcd, local bus, or maximum isa bus controller depending on the configuration chosen, the lansc300 microcontrollers pin functionality will differ. the three different options are internal cga controller, local bus, and maximum isa bus modes. the pin op- tions are selected upon power-up reset. only internal cga, local bus, or maximum isa bus mode is avail- able in a particular design. both internal cga and local bus modes do, however, provide a subset of the isa bus. the three sets of pin descriptions are described in al- ternate pin functions selected via firmware on page 71. internal cga controller option the internal video controller is fully 6845 compatible, supporting up to 640 x 200 pixel lcd panels. this op- tion supports an external 32-kbyte sram for video memory. the smallest subset of the isa bus is avail- able when using the internal cga controller. local bus option the local bus interface is integrated with the memory controller and the isa bus controller, and it permits fast transfers to and from external local bus peripherals, such as video controllers. the local bus option is basi- cally an am386sxlv microprocessor local bus with an ldev , lrdy , and cpuclk added. additional isa bus signals are available in this mode. maximum isa bus option the maximum isa option provides the most isa bus signals of any of the lansc300 microcontroller bus options. since master cycles and isa refresh are not necessary in handheld designs, the lansc300 micro- controller does not provide these signals in any bus mode. the sysclk output from the lansc300 micro- controller is a clock that is normally only used for the external keyboard controller if one exists. this clock is 9.2 mhz and can be stopped completely. this clock is not related to any of the isa bus cycle tim- ings. the isa bus cycle timings vary depending on the clock speed selected for the internal isa bus clock. internal resistors the lansc300 microcontrollers internal pull-down and pull-up resistors are approximately 100-k w 50% tolerance. they dont provide the level of termination that may be necessary to meet design noise margins or the timing and termination requirements for different bus specifications (e.g., isa bus or local bus). the internal pull-up and pull-down resistors only pro- vide adequate termination for when the input is floating and is in a very low noise environment, or for systems where power consumption is too critical to allow for the additional current associated with stronger pullups. be- cause of this, it is recommended that the designer use the external pull-up and pull-down resistors (shown in table 26) on signals with critical timing or noise immu- nity requirements. the external pull-up and pull-down resistors are also recommended for additional design margin, provided that space and power consumption are not major issues. table 26. external resistor requirements signal name pin no. internal cga local bus maximum isa notes pull up pull down pull up pull down pull up pull down pirq0 (pirq0/irq3) 194 10k 10k 10k pirq1 (pirq1/irq6) 193 10k 10k 10k irq1 195 10k 10k 10k iochrdy 192 1k 1k 1k iocs16 [lcddl0] 196 1k[C] 1k[C] 1k[C] 1 mcs16 [lcddl1] 197 1k[C] 1k[C] 1k[C] 1 irq14 [lcddl2] 198 10k[C] 10k 10k 1 dtr /cfg1 92 100k 10k 100k 2 rts /cfg0 93 100k 100k 10k 2 ioreset 140 10k 10k 10k 66 lan?sc300 microcontroller data sheet preliminary signal name pin no. internal cga local bus maximum isa notes pull up pull down pull up pull down pull up pull down lvee (irq15/irq15) 182 10k 10k m (irq4/irq4) 173 10k 10k lcdd2 (iochchk /iochchk ) 177 1k 1k dswe (pullup/pullup) 183 100k 100k frm (irq12/irq12) 181 10k 10k cp2 (pullup/irq10) 179 1k 10k dsma1 (pullup/irq7) 164 10k 10k dsmd0 (ldev /reserved) 148 1k lcdd3 (drq1/ drq1) 174 10k 10k 3 lcdd1 (drq5/ drq5) 175 10k 10k 3 cp1 (pulldn/ irq5) 178 10k 10k dsmd7 (ads /0ws ) 172 1k dsmd3 (bhe /irq9) 168 10k dsmd2 (ble /irq11) 167 10k dsma3 (cpuclk/pullup) 162 1m dsma0 (nc/pullup) 165 1m dsmd6 (d/c / drq0) 171 10k 3 dsmd5 (m/io / drq3) 170 10k 3 dsmd4 (w/r / drq7) 169 10k 3 dsmd1 (lrdy / drq6) 166 1k 10k 3 drq2 [tdo] 76 10k 10k 10k 3 bvd2_a 113 10k 10k 10k 4 bvd1_a 114 10k 10k 10k 4 bvd2_b 119 10k 10k 10k 4 bl1 106 100k 100k 100k 5 bl2 107 100k 100k 100k 5 bl3 108 100k 100k 100k 5 bl4 109 100k 100k 100k 5 sout 94 10k rst_a 133 100k 100k 100k rst_b 127 100k 100k 100k bvd1_b 120 10k 10k 10k 4 wait_ab 115 10k 10k 10k 4 cd_a 110 10k 10k 10k 4 cd_b 116 10k 10k 10k 4 table 26. external resistor requirements (continued) lan?sc300 microcontroller data sheet 67 preliminary notes: all pull-up and pull-down resistor requirements are specified in ohms. 1. a [C] implies that for this programmable pin function, no external termination is required. 2. this pin is an alternate pin function select input that is sampled at reset. this pin functions as a normal serial port output after resin and ioreset are deasserted. 3. when this pins function is a dma request input, it should be terminated with a pull-down resistor if not connected to an ex- ternal device that drives to a known state. 4. if this lansc300 microcontroller input is driven directly with a logic gate, then no external termination is required at the lansc300 microcontroller pin. the termination on the pcmcia socket signal is still required per the pcmcia 2.1 specifica- tion. 5. if this lansc300 microcontroller input is always driven to a known state, then no external termination is required. 6. if the pin is configured as an input, it should be terminated with a discrete pull-up or pull-down resistor, or it should always be driven to a known state. signal name pin no. internal cga local bus maximum isa notes pull up pull down pull up pull down pull up pull down rdy_a 111 10k 10k 10k 4 rdy_b 117 10k 10k 10k 4 wp_a 112 10k 10k 10k wp_b 118 10k 10k 10k dcd 98 1m 1m 1m dsr 97 1m 1m 1m sin 99 1m 1m 1m cts 96 1m 1m 1m rin 100 1m 1m 1m strb 83 4.7k 4.7k 4.7k afdt 80 4.7k 4.7k 4.7k init 89 4.7k 4.7k 4.7k slctin 84 4.7k 4.7k 4.7k error 86 4.7k 4.7k 4.7k ack 88 4.7k 4.7k 4.7k busy 85 4.7k 4.7k 4.7k pe 82 4.7k 4.7k 4.7k slct 87 4.7k 4.7k 4.7k pgp0 189 100k 100k 100k 6 pgp1 188 100k 100k 100k 6 acin 101 10k 10k 10k 5 table 26. external resistor requirements (continued) 68 lan?sc300 microcontroller data sheet preliminary alternate pin functions to provide the system designer with the most flexibility, the lansc300 microcontroller provides a means for reconfiguring some of the pin functions, depending on the system requirements. reconfiguration of the lansc300 microcontroller pin functions is accom- plished in one of two ways, depending on the pin func- tions that are to be reconfigured. to select the internal lcd controller, cpu local bus interface, or maximum isa bus interface, the state of the dtr and rts pins are sampled on the rising edge of the resin and ioreset signals when power is first applied to the lansc300 microcontroller. this is shown in figure 8. after power has been initially applied and resin and ioreset are deasserted, additional assertions of ioreset while resin = 1 will not cause the pin con- figurations to change. however, the pin configuration inputs are always sampled in response to resin as- sertions. table 27 shows the pin states at reset to en- able the three different pin configurations involving the lcd controller, local bus, and maximum isa bus. the bus configuration selected can be read in bits 5C6 of the memory configuration 1 register, index 66h, after the reset. the second method of reconfiguring lansc300 micro- controller pin functions is accomplished by program- ming the internal configuration registers. this method is used to configure the following functions: n dram or sram main memory interface n dual-scan lcd interface n unidirectional or bidirectional parallel port n the clock source driving the x1out[baudout] pin n pcmcia memory commands n 14.336-mhz clock table 27. bus option select bit logic bus selected dtr /cfg1 rts /cfg0 internal lcd 00 local bus 10 full/maximum isa x1 vcc resi n and iorese t rts dtr d tr and rts sampled at the rising edge of resin and ioreset notes: this is shown to illustrate when cfg0 and cfg1 are sampled and is not intended to be used for reset timings. for reset timings, refer to table 51 on page 99 figure 8. bus option configuration select lan?sc300 microcontroller data sheet 69 preliminary cpu local bus interface versus internal lcd interface the tables of this section are brief descriptions of the alternate pin functions/names and the pin name of the internal lcd mode function that the alternate function replaces. the cpu local bus interface alternate functions are con- figured via the dtr and rts pin states when the lansc300 microcontroller is reset. notes: 1. the sa11Csa0 pins are the lower order address lines for local bus cycles in the local bus interface mode. 2. see the table 26 on page 65 for information on required termination for local bus and internal lcd controller modes. 3. other internal lcd controller mode pin functions, which are not listed in this table, change when the local bus mode is en- tered. these pins change to an isa bus function when local bus mode is entered. table 28. pins shared between cpu local bus and internal lcd interface functions cpu local bus interface pin name pin type cpu local bus interface pin description/notes internal lcd controller mode function pin name pin no. a23Ca12 o local bus address bus dsma14Cdsma4 lvdd 145 149C155 158C161 ads o address strobe dsmd7 172 d/c o data/code cycle status signal dsmd6 171 m/io o memory/i/o cycle status signal dsmd5 170 w/r o write/read cycle status signal dsmd4 169 bhe o byte high enable dsmd3 168 ble o byte low enable dsmd2 167 lrdy i local device ready dsmd1 166 ldev i local bus device acknowledge dsmd0 148 cpurdy o cpu ready dsoe 147 cpuclk o cpu clock dsma3 162 cpurst o cpu reset dsma2 163 70 lan?sc300 microcontroller data sheet preliminary maximum isa interface versus internal lcd interface the maximum isa interface alternate functions are configured via the dtr and rts pin states when the lansc300 microcontroller is reset. notes: see the external resistor requirements section for information on required termination for maximum isa bus and internal lcd controller modes. table 29. pins shared between maximum isa bus and internal lcd interface functions isa interface pin name pin type isa interface pin description/notes internal lcd controller mode function pin name pin no. iochchk i isa i/o channel check input lcdd2 177 bale o isa bus address latch enable lvdd 145 drq0 i dma channel 0 request dsmd6 171 drq1 i dma channel 1 request lcdd3 174 drq3 i dma channel 3 request dsmd5 170 drq5 i dma channel 5 request lcdd1 175 drq6 i dma channel 6 request dsmd1 166 drq7 i dma channel 7 request dsmd4 169 dack0 o dma channel 0 acknowledge dsma7 158 dack1 o dma channel 1 acknowledge dsce 146 dack3 o dma channel 3 acknowledge dsma6 159 dack5 o dma channel 5 acknowledge lcdd0 144 dack6 o dma channel 6 acknowledge dsma4 161 dack7 o dma channel 7 acknowledge dsma5 160 irq4 i interrupt request input m 173 irq5 i interrupt request input cp1 178 irq7 i interrupt request input dsma1 164 irq9 i interrupt request input dsmd3 168 irq10 i interrupt request input cp2 179 irq11 i interrupt request input dsmd2 167 irq12 i interrupt request input frm 181 irq15 i interrupt request input lvee 182 la23Cla17 o isa non-latched address bus dsma14Cdsma8 149C155 lmeg o isa memory address decode below 1 mbyte dsoe 147 0ws i zero wait state dsmd7 172 lan?sc300 microcontroller data sheet 71 preliminary alternate pin functions selected via firmware the following tables contain brief descriptions of the alternate pin functions/names and the pin names of the default function that the alternate function replaces. these alternate functions are selected via system firmware only. sram interface this alternate function is configured by setting bit 0 of the miscellaneous 6 register, index 70h. dual-scan lcd data bus this alternate function is configured via selecting a dual-scan lcd panel mode in the cga index address space at index 18h. notes: in the dual-scan lcd configuration, iocs16 and mcs16 are internally forced inactive. unidirectional/bidirectional parallel port this alternate function is configured via selecting either the normal bidirectional mode configuration or the epp mode configuration for the parallel port in the function enable 1 register, index b0h. table 30. sram interface sram pin name pin type sram interface pin description/notes default pin name/function pin no. [srcs0 ] o sram bank 0 chip select. low byte cas0l 6 [srcs1 ] o sram bank 0 chip select. high byte cas0h 7 [srcs2 ] o sram bank 1 chip select. low byte cas1l 4 [srcs3 ] o sram bank 1 chip select. high byte cas1h 5 table 31. dual-scan lcd data bus dual-scan pin name pin type dual-scan lcd data-bus pin description/notes default pin name/function pin no. [lcddl0] o dual screen data bit iocs16 196 [lcddl1] o dual screen data bit mcs16 197 [lcddl2] o dual screen data bit irq14 198 [lcddl3] o dual screen data bit sbhe 143 table 32. bidirectional parallel port pin description bidirectional pin name pin type bidirectional parallel port pin description/notes default pin name/function pin no. [ppdcs ] o parallel port data register address decode ppdwe 90 72 lan?sc300 microcontroller data sheet preliminary x1out [baud_out] clock source the internal clock source driving out on this pin is configured via register bits of the function enable registers, indexes b0h and b1h. notes: the default function of this pin is that no clock is driven out and the pin is tri-stated. pc/xt keyboard the pc/xt keyboard functionality is enabled via bit 3 of pmu control 3 register, index adh. pcmcia data path control setting bit 4 of miscellaneous 3 register, index bah, enables the pcmcia memory commands on the parallel port pins slctin and init. 14-mhz clock source setting bit 3 of miscellaneous 3 register, index bah, enables the 14.336-mhz clock signal on the parallel port pin afdt. table 33. x1out clock source pin description baudout pin name pin type x1out [baud_out] pin description/notes default pin name/function pin no. [baud_out] o serial baud rate clock x1out 200 table 34. xt keyboard pin description pc/xt keyboard pin name pin type pc/xt keyboard pin description/notes default pin name/function pin no. [xtdat] i/o keyboard data 8042cs 75 [xtclk] i/o keyboard clock sysclk 45 table 35. pcmcia data path control pcmcia control pin name pin type data path control pin description/notes default pin name/ function pin no. [pcmcoe ] o pcmcia output enable slctin 84 [pcmcwe ] o pcmcia write enable init 89 table 36. 14-mhz clock source 14-mhz pin name pin type 14-mhz clock pin description/notes default pin name/ function pin no. [x14out] o 14.336 mhz clock afdt 80 lan?sc300 microcontroller data sheet 73 preliminary isa bus descriptions the three bus configuration options (internal lcd con- troller, local bus, or maximum isa bus) each support a somewhat different subset of the isa bus standard. the internal lcd controller option supports the small- est isa subset, defined in table 37. notes: 1. these isa functions are available in this mode as long as the internal lcd controller is not configured for a dual- scan lcd panel in which case these pins would be used as additional data bits for the lcd panel. in local bus mode and maximum isa mode, the isa function is always available. the local bus configuration supports a larger isa sub- set. the additional pins supported are shown in table 38. the maximum isa bus configuration adds the pins found in table . table 37. internal lcd controller bus mode isa bus functionality pin name i/o function sa23Csa0 o system address bus d15Cd0 b system data bus iochrdy i i/o channel ready rstdrv o system reset memw o memory write memr o memory read iow o i/o write ior o i/o read aen o dma address enable tc o terminal count sysclk o system clock (isa bus timing is not derived from this clock) irq1 i interrupt irq1 pirq0 i programmable irqx pirq1 i programmable irqx dack2 o dma channel 2 acknowledge drq2 i dma channel 2 request iocs16 i i/o device is 16 bits 1 mcs16 i memory device is 16 bits 1 irq14 i interrupt request input 1 sbhe o byte high enable 1 x1out [baudout] o video oscillator (14.336 mhz)/ serial port output table 38. local bus mode additional isa bus functionality pin name i/o function iochchk i isa i/o channel check drq1 i dma channel 1 request dack1 o dma channel 1 acknowledge drq5 i dma channel 5 request dack5 o dma channel 5 acknowledge irq4 i interrupt request input irq12 i interrupt request input irq15 i interrupt request input table 39. maximum isa bus mode additional isa bus functionality pin name i/o function bale o isa bus address latch enable dreq0 i dma channel 0 request dreq3 i dma channel 3 request dreq6 i dma channel 6 request dreq7 i dma channel 7 request dack0 o dma channel 0 acknowledge dack3 o dma channel 3 acknowledge dack6 o dma channel 6 acknowledge dack7 o dma channel 7 acknowledge irq7 i interrupt request input irq9 i interrupt request input irq11 i interrupt request input 0ws i zero wait state request la23Cla17 o isa non-latched address lmeg o isa memory cycle below 100000h irq5 i interrupt request input irq10 i interrupt request input 74 lan?sc300 microcontroller data sheet preliminary system test and debug the lansc300 microcontroller provides test and debug features compatible with the standard test ac- cess port (tap) and boundary-scan architecture (jtag). the test and debug logic contains the following ele- ments: n five extra pinstdi, tms, tck, tdo, and trst (jtagen). jtagen is dedicated; the other four are multiplexed. n test access port (tap) controller, which decodes the inputs on the test mode select (tms) line to control test operations. n instruction register (ir), which accepts instructions from the test data input (tdi) pin. the instruction codes select the specific test or debug operation to be performed or the test data register to be ac- cessed. n test data registers: boundary scan register (bsr), device identification register (did), and by- pass register (bpr). test access port (tap) controller the tap controller is a synchronous, finite state ma- chine that controls the sequence of operations of the test logic. the tap controller changes state in re- sponse to the rising edge of tck and defaults to the test-logic-reset state at power-up. reinitialization to the test-logic-reset state is accomplished by holding the tms pin high for five tck periods. instruction register the instruction register is a 4-bit register that allows instructions to be serially shifted into the device. the in- struction determines either the test to execute or the data register to access, or both. the least significant bit is nearest the tdo output. when the tap controller en- ters the capture-ir state, the instruction register is loaded with the default instruction idcode. this is done to test for faults in the boundary scan connections at the board level. boundary scan register the boundary scan register is a serial shift register from tdi to tdo, consisting of all the boundary scan register bits and control cells in each i/o buffer. device identification register the device identification register is a 32-bit register that contains the amd id code for the lansc300 mi- crocontroller: 195fa003h. bypass register the bypass register provides a path from tdi to tdo with one clock cycle latency. it helps to bypass a chip completely while testing boards containing many chips. test access port instruction set the following instructions are supported: n sample/preload. this instruction enables the sam- pling of the contents of the boundary scan registers as well as the serial loading of the boundary scan registers through tdi. n bypass. this instruction connects tdi and tdo through a 1-bit shift register, the bypass register. n extest. this instruction enables the parallel loading of the boundary scan registers. the device inputs are captured at the input boundary scan cell and the device outputs are captured at the output boundary scan cells. n idcode. this instruction connects the id code reg- ister between tdi and tdo. the id code register contains the fixed id code value for the device. jtag software the lansc300 microcontroller uses combined bidi- rectional cells. the total number of shifts required to load the lansc300 boundary scan register is 173. the following table shows the relative position of all the lansc300 jtag cells. note that: n the chain starts at pmc2 (pin 77) connected to tdi. n the chain ends at 8042cs (pin 75) connected to tdo. n the control cells are located within the chain, their relative position being indicated in the table. n the muxed signals (tck, tdi, tdo, and tms) are not part of the cell chain. n control cells are active low. n refer to figure 10C22 of the ieee 1149 standard. lan?sc300 microcontroller data sheet 75 preliminary table 40. boundary scan (jtag) cellsorder and type pin no. name cell position cell type notes 77 pmc2 1 output 78 rc 2 input 79 a20gate 3 input 80 afdt 4output 82 pe 5 input 83 strb 6output 84 slctin 7output 85 busy 8 input 86 error 9 input 87 slct 10 input 88 ack 11 input 89 init 12 output 90 ppdwe 13 bidir 91 ppoen 14 bidir 92 dtr 15 bidir 93 rts 16 bidir 94 sout 17 bidir 96 cts 18 input 97 dsr 19 input 98 dcd 20 input 99 sin 21 input 100 rin 22 input 101 acin 23 input 102 extsmi 24 input 103 sus/res 25 input * * 26 control control cell for pins 106C155 106 bl1 27 input 107 bl2 28 input 108 bl3 29 input 109 bl4 30 input 110 cd_a 31 input 111 rdy_a 32 input 112 wp_a 33 input 113 bvd2_a 34 input 114 bvd1_a 35 input 115 wait_ab 36 input 116 cd_b 37 input 117 rdy_b 38 input 118 wp_b 39 input 119 bvd2_b 40 input 120 bvd1_b 41 input 122 icdir 42 output 76 lan?sc300 microcontroller data sheet preliminary 123 mcel_b 43 output 124 mceh_b 44 output 125 vpp_b 45 output 126 reg_b 46 output 127 rst_b 47 output 129 mcel_a 48 output 130 mceh_a 49 output 131 vppa 50 output 132 reg_a 51 output 133 rst_a 52 output 134 ca24 53 output 136 ca25 54 output 137 pmc0 55 output 138 pmc1 56 output 139 spkr 57 output 140 ioreset 58 input 141 resin 59 input 143 sbhe 60 output 144 lcdd0 61 output 145 lvdd 62 output 146 dsce 63 output 147 dsoe 64 output 148 dsmd0 65 bidir 149 dsma14 66 output 150 dsma13 67 output 151 dsma12 68 output 152 dsma11 69 output 153 dsma10 70 output 154 dsma9 71 output 155 dsma8 72 output * * 73 control control cell for pins 158C200 158 dsma7 74 output 159 dsma6 75 output 160 dsma5 76 output 161 dsma4 77 output 162 dsma3 78 output 163 dsma2 79 output 164 dsma1 80 bidir 165 dsma0 81 output 166 dsmd1 82 bidir 167 dsmd2 83 bidir 168 dsmd3 84 bidir 169 dsmd4 85 bidir table 40. boundary scan (jtag) cellsorder and type (continued) pin no. name cell position cell type notes lan?sc300 microcontroller data sheet 77 preliminary 170 dsmd5 86 bidir 171 dsmd6 87 bidir 172 dsmd7 88 bidir 173 m 89 bidir 174 lcdd3 90 bidir 175 lcdd1 91 bidir 177 lcdd2 92 bidir 178 cp1 93 bidir 179 cp2 94 bidir 181 frm 95 bidir 182 lvee 96 bidir 183 dswe 97 bidir 184 pmc4 98 output 185 pmc3 99 output 186 pgp3 100 bidir 187 pgp2 101 bidir 188 pgp1 102 bidir 189 pgp0 103 bidir 190 lph 104 output 191 iochrdy 105 input 193 pirq(1) 106 input 194 pirq(0) 107 input 195 irq1 108 input 196 iocs16 109 bidir 197 mcs16 110 bidir 198 irq14 111 bidir 200 clk14_o 112 output * * 113 control control cell for pins 2C51 2 ras0 114 output 3 ras1 115 output 4 cas1l 116 output 5 cas1h 117 output 6 cas0l 118 output 7 cas0h 119 output 8mwe 120 output 10 ma10 121 output 11 ma9 122 output 13 ma8 123 output 14 ma7 124 output 15 ma6 125 output 16 ma5 126 output 17 ma4 127 output 18 ma3 128 output table 40. boundary scan (jtag) cellsorder and type (continued) pin no. name cell position cell type notes 78 lan?sc300 microcontroller data sheet preliminary 19 ma2 129 output 21 ma1 130 output 24 ma0 131 output 25 d15 132 bidir 26 d14 133 bidir 27 d13 134 bidir 28 d12 135 bidir 29 d11 136 bidir 30 d10 137 bidir 31 d9 138 bidir 32 d8 139 bidir 34 d7 140 bidir 36 d6 141 bidir 37 d5 142 bidir 38 d4 143 bidir 39 d3 144 bidir 40 d2 145 bidir 41 d1 146 bidir 42 d0 147 bidir 43 doscs 148 output 44 romcs 149 output 45 sysclk 150 bidir 46 dack2 * this pin becomes tck when jtagen is high. 47 aen * this pin becomes tdi when jtagen is high. 49 tc * this pin becomes tms when jtagen is high. 50 endirl 151 output 51 endirh 152 output * * 153 control control cell for pins 54C103 54 ior 154 output 55 iow 155 output 56 memr 156 output 57 memw 157 output 58 rstdrv 158 output 59 dbufoe 159 output 60 sa12 160 output 61 sa11 161 output 62 sa10 162 output 63 sa9 163 output 64 sa8 164 output 66 sa7 165 output 67 sa6 166 output 69 sa5 167 output 70 sa4 168 output table 40. boundary scan (jtag) cellsorder and type (continued) pin no. name cell position cell type notes lan?sc300 microcontroller data sheet 79 preliminary jtag instruction opcodes table 41 l ists the lansc300 microcontrollers public jtag instruction opcodes. note that the jtag instruction reg- ister is 4 bits wide. 71 sa3 169 output 72 sa2 170 output 73 sa1 171 output 74 sa0 172 output 75 8042cs 173 bidir 76 drq2 * this pin becomes tdo when jtagen is high. table 41. lansc300 microcontroller jtag instruction opcodes instruction opcode extest 0000 bypass 1111 sample/preload 0001 idcode 0010 hi-z 0011 table 40. boundary scan (jtag) cellsorder and type (continued) pin no. name cell position cell type notes 80 lan?sc300 microcontroller data sheet preliminary absolute maximum ratings storage temperature ....................... C65 c to +150 c ambient temperature under bias ... C65 c to +125 c supply voltage v cc with respect to v ss ................................C0.5 v to +7 v voltage on other pins...............C0.5 v to (v cc +0.5 v) stresses above those listed may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges operating ranges define those limits between which the functionality of the device is guaranteed. table 42. dc characteristics over commercial and industrial operating ranges (plastic shrink quad flat pack (qfp), 33 mhz, 3.3 v) vccio = 3.0 v C 3.6 v; t ambient = 0 c to +70 c (commercial); t case = -40 to +85c (industrial) notes: 1. current out of a pin is given as a negative value. 2. vcc, vcc1, avcc = 3.3 v and vcc5, vccsys, vccsys2 = 5.0 v. 3. fc = 1 mhz. symbol parameter description preliminary unit min typ max f osc frequency of operation (internal cpu clock) 033mhz p cc 2 supply powercpu clock = 33 mhz (vccmem=3.3 v) 582 778 mw p ccss 2 suspend powercpu idle, all internal clocks stopped except 32.768 khz 0.12 mw v oh(cmos) output high voltage i oh(cmos) = C0.5 ma vccC 0.45 v v ol(cmos) output low voltage i ol(cmos) = 0.5 ma 0.45 v v ih(cmos) input high voltage 2.0 vcc+0.3 v v il(cmos) input low voltage C0.3 +0.8 v i li input leakage current (0.1 v v out vcc) (all pins except those with internal pull-up/pull-down resistors) 10 m a i ih input leakage current v ih = vcc C 0.1 v (all pins with internal pull-down resistors) 60 m a i il input leakage current v il = 0.1 v (pins with internal pull-up resistors) C60 m a i lo output leakage current (0.1 v v out vcc) 15 m a c in 3 i/o capacitance 15 pf avcc rpCp analog v cc ripple peak to peak 100 mv lan?sc300 microcontroller data sheet 81 preliminary table 43. dc characteristics over commercial and industrial operating ranges (plastic shrink quad flat pack (qfp), 33 mhz, 5 v) vccio = 4.5 v C 5.5 v; t ambient = 0 c to +70 c (commercial); t case = -40 to +85c (industrial) notes: 1. current out of a pin is given as a negative value. 2. vcc, vcc1, avcc = 3.3 v and vcc5, vccsys, vccsys2 = 5 v. 3. fc = 1 mhz. notes: 1.vcc and avcc are 3.3 v only. symbol parameter description preliminary unit min typ max f osc frequency of operation (internal cpu clock) 033mhz p cc 2 supply powercpu clock = 33 mhz (vccmem=5 v) 660 862 mw p ccsb 2 suspend powercpu idle, all internal clocks stopped except 32.768 khz 0.17 mw v oh(cmos) output high voltage i oh(cmos) = C 0.5 ma vccC0.45 v v ol(cmos) output low voltage i ol(cmos) = 0.5 ma 0.45 v v ih(cmos) input high voltage 2.0 vcc+0.3 v v il(cmos) input low voltage C0.3 +0.8 v i li input leakage current (0.1Cv v out vcc) (all pins except those with internal pull-up/pull-down resistors) 10 m a i ih input leakage current v ih = vcc C 0.1 v (all pins with internal pull-down resistors) 90 m a i il input leakage current v il = 0.1 v (pins with internal pull-up resistors) C90 m a i lo output leakage current (0.1Cv v out vcc) 15 m a c in (3) i/o capacitance 15 pf avcc rp-p analog vcc ripple peak to peak (3.3 v only) 100 mv table 44. commercial and industrial operating voltage ranges at 25 power pin name 3.0 vC3.6 v 4.5 vC5.5 v vcc 1 ? n/a vcc1 ?? avcc 1 ? n/a vcc5 ?? vccmem ?? vccsys2 ?? 82 lan?sc300 microcontroller data sheet preliminary thermal characteristics the lansc300 microcontroller is specified for operation with a case temperature range from 0c to 100c for a commercial device. table 45 shows the thermal resistance for 208-pin qfp and tqfp packages. typical power numbers table 46 and table 47 show the typical power numbers that were measured for the lansc300 microcontroller. these measurements reflect the part when it is config- ured for maximum isa and internal cga modes of op- eration at operating speeds of 33 mhz, 25 mhz, and 9.2 mhz. the connection of the various power sections of the part are outlined in the tables so that the designer may have some relative information for the power con- sumption differences between 3.3 v operation and 5 v operation. please see the notes associated with the ta- bles for specifics on the test conditions. table 45. thermal resistance (c/watt) y jt and q ja for 208-pin qfp and tqfp packages package y jt q ja vs. airflow-linear ft/min. (m/s) 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) qfp 4.7 33 26 25 23 22 tqfp 7 37.4 31.0 28.5 26.9 26.6 table 46. typical maximum isa mode power consumption power pin maximum isa mode group name volts 33 mhz 25 mhz 9.2 mhz doze 2 suspend 3 m pwr off 4 cpu core vcc 3.3 119 ma 94.3ma 39.1ma 6.12 ma 5.7 m a4.1 m a i/o vcc vcc1 5 5.55 ma 5.55ma 5.55ma 5.55 ma 0 m a off analog avcc 3.3 2.58 ma 2.36 ma 2.24 ma 1.39 ma 19.9 m a19.8 m a i/o vcc5 5 772 m a 680 m a 434 m a 293 m a0 m a off memory vccmem 3.3 16.4 ma 12.6 ma 4.9 ma 190 m a 10.5 m a off sub isa bus vccsys 5 16.8 ma 13.7 ma 7.76 ma 3.6 ma 0 m a off full isa bus vccsys2 5 2.06 ma 1.57 ma 0.9 ma 21 m a0 m a off total (mw) 582 mw 468mw 226mw 72.7 mw 0.12 mw 0.08 mw memory 5 vccmem 5 26.5 ma 20.3 ma 8.75 ma 304 m a 17 m a off total (mw) 660 mw 528 mw 470 mw 73.6 mw 0.17 mw 0.08 mw see notes on page 83. lan?sc300 microcontroller data sheet 83 preliminary notes: all measurements were obtained at typical room temperature (ambient). 1. in normal operating mode measurements, the lansc300 microcontroller is running the landmark speedcom benchmark (version 2.00). all cpu idle cycles are run at the high-speed rate. 2. in doze mode, the doze mode configuration is such that the low-speed cpu clock is programmed to turn on for 64 refresh cycles upon an irq0 (dos timer) generation. after 64 refresh cycles, the low-speed cpu clock is turned off again. the irq0 timer is set for an approximate 55 ms interval and the refresh duty cycle is approximately 15.6 m s. in doze mode, the high- speed pll is always turned off and, in this case, the low-speed pll and video plls are on to allow the irq0 periodic wake- up. 3. suspend mode measurements were taken with dram refresh rate set at 8192 hz (126 m s). 4. micropower measurements were taken with dram unpowered and the dram refresh rate set at 8192 hz. 5. these measurements were taken with the memory interface powered at 5 v, rather than 3.3 v. table 47. typical internal lcd mode power consumption t a = 70 c, v ol ttl = 0.4 v, v oh ttl = 2.4 v power pin internal cga mode group name volts 33 mhz 25 mhz 9.2 mhz doze 2 suspend 3 m pwr off 4 cpu core vcc 3.3 121 ma 95.2 ma 40.1 ma 6.24 ma 5.5 m a4.1 m a i/o vcc vcc1 5 14.8 ma 14.8 ma 14.8 ma 14.7 ma 0 m a off analog avcc 3.3 2.62 ma 2.4 ma 2.24 ma 1.4 ma 19.9 m a19.8 m a i/o vcc5 5 867 m a 765 m a 562 m a 448 m a0 m a off memory vccmem 3.3 17 ma 13 ma 4.9 ma 182 m a 11.3 m a off sub isa bus vccsys 5 18.9 ma 15.3 ma 8.1 ma 3.85 ma 0 m a off full isa bus vccsys2 5 3.88 ma 3.86 ma 3.82 ma 3.79 ma 0 m a off total (mw) 656 mw 539 mw 292 mw 140 mw 0.12 mw 0.08 mw memory 5 vccmem 5 26.8 ma 20.4 ma 7.6 ma 300 m a 17.6 m a off total (mw) 734 mw 598 mw 314 mw 141 mw 0.17 mw 0.08 mw 84 lan?sc300 microcontroller data sheet preliminary derating curves this section describes how to use the derating curves on the following pages in order to determine potential specified timing variations based on system capacitive loading. the pin characteristics tables in this document (see page 24 ) have a column called spec. load. this column describes the specification load presented to the specific pin when testing was performed to gener- ate the timing specification documented in ac switch- ing characteristics and waveforms on page 98. for example, to find out the effect of capacitive loading on a dram specification such as mwe hold from cas low, first find the specification load for mwe from the pin characteristics table. the value here is 70 pf. note the output drive type is d. also, assume that the system dram interface is 3.3 v and our system load on the lansc300 microcontrollers mwe pin is 90 pf. referring to figure 13, 3.3 v i/o drive type d rise time, a time value of approximately 9.8 ns corresponds to a capacitive load of 70 pf. also referring to figure 13, a time value of approxi- mately 12.3 ns corresponds to a capacitive load of 90 pf. subtracting 9.8 ns from the 12.3 ns, it can be seen that the rise time on the mwe signal will increase by 2.5 ns. therefore, the mwe hold from cas low (min) parameter will increase from 15 ns to 17.5 ns (15 ns + 2.5 ns). if the capacitive load on mwe was less than 70 pf, the time given in the derating curve for the load would be subtracted from the time given for the specification load. this difference can then be subtracted from the mwe hold from cas low (min) parameter (isns) to determine the derated ac timing parameter. table 48. i/o drive type description (worst case) notes: 1. current out of pin is given as a negative value. t a = 70 c, v ol ttl = 0.4 v, v oh ttl = 2.4 v i/o drive type vccio (v) iol ttl (ma) ioh ttl (ma) 1 a3.0 4.5 2.6 3.7 C3.5 C13.9 b3.0 4.5 5.1 7.3 C5.2 C20.7 c3.0 4.5 7.7 10.8 C8.6 C34.2 d3.0 4.5 7.7 10.8 C10.3 C40.8 e3.0 4.5 10.2 14.1 C13.6 C53.9 lan?sc300 microcontroller data sheet 85 preliminary time (ns) 0 2 4 6 8 10 12 10 20 30 40 50 60 70 80 90 100 load (pf) figure 9. 3.3-v i/o drive type e rise time 0 2 4 6 8 10 12 10 20 30 40 50 60 70 80 90 100 load (pf) time (ns) figure 10. 3.3-v i/o drive type e fall time 86 lan?sc300 microcontroller data sheet preliminary 0 1 2 3 4 5 6 7 8 10 20 30 40 50 60 70 80 90 100 load (pf) time (ns) figure 11. 5-v i/o drive type e rise time 0 1 2 3 4 5 6 7 8 9 10 20 30 40 50 60 70 80 90 100 load (pf) time (ns) figure 12. 5-v i/o drive type e fall time lan?sc300 microcontroller data sheet 87 preliminary 0 2 4 6 8 10 12 14 16 18 20 10 20 30 40 50 60 70 80 90 100 120 130 140 load (pf) time (ns ) figure 13. 3.3-v i/o drive type d rise time 0 5 10 15 20 25 10 20 30 40 50 60 70 80 90 100 120 130 140 load (pf) time (ns) figure 14. 3.3-v i/o drive type d fall time 88 lan?sc300 microcontroller data sheet preliminary 0 2 4 6 8 10 12 14 16 10 20 30 40 50 60 70 80 90 100 120 130 140 150 load (pf) time (ns) figure 15. 5-v i/o drive type d rise time 0 2 4 6 8 10 12 14 16 18 10 20 30 40 50 60 70 80 90 100 120 130 140 150 load (pf) time (ns) figure 16. 5-v i/o drive type d fall time lan?sc300 microcontroller data sheet 89 preliminary 0 2 4 6 8 10 12 14 10 20 30 40 50 60 70 80 load (pf) time (ns) figure 17. 3.3-v i/o drive type c rise time 0 2 4 6 8 10 12 10 20 30 40 50 60 70 80 load (pf) time (ns) figure 18. 3.3-v i/o drive type c fall time 90 lan?sc300 microcontroller data sheet preliminary 0 1 2 3 4 5 6 7 8 9 10 10 20 30 40 50 60 70 80 load (pf) time (ns) figure 19. 5-v i/o drive type c rise time 0 1 2 3 4 5 6 7 8 9 10 20 30 40 50 60 70 80 load (pf) time (ns) figure 20. 5-v i/o drive type c fall time lan?sc300 microcontroller data sheet 91 preliminary 0 5 10 15 20 25 10 20 30 40 50 60 70 80 load (pf) time (ns) figure 21. 3.3-v i/o drive type b rise time 0 2 4 6 8 10 12 14 16 18 10 20 30 40 50 60 70 80 load (pf) time (ns) figure 22. 3.3-v i/o drive type b fall time 92 lan?sc300 microcontroller data sheet preliminary 0 2 4 6 8 10 12 14 16 10 20 30 40 50 60 70 80 load (pf) time (ns) figure 23. 5-v i/o drive type b rise time 0 2 4 6 8 10 12 14 10 20 30 40 50 60 70 80 load (pf) time (ns) figure 24. 5-v i/o drive type b fall time lan?sc300 microcontroller data sheet 93 preliminary 0 5 10 15 20 25 30 35 10 20 30 40 50 60 70 80 load (pf) time (ns) figure 25. 3.3-v i/o drive type a rise time 0 5 10 15 20 25 30 35 10 20 30 40 50 60 70 80 load (pf) time (ns) figure 26. 3.3-v i/o drive type a fall time 94 lan?sc300 microcontroller data sheet preliminary 0 5 10 15 20 25 10 20 30 40 50 60 70 load (pf) time (ns) figure 27. 5-v i/o drive type a rise time 80 0 5 10 15 20 25 30 10 20 30 40 50 60 70 80 load (pf) time (ns) figure 28. 5-v i/o drive type a fall time lan?sc300 microcontroller data sheet 95 preliminary voltage partitioning the lansc300 microcontroller supports both 3.3-v system designs and mixed 3.3-v and 5-v system de- signs. for 3.3-v-only operation, all supply pins (vcc, vcc1, vcc5, vmem, vsys, vsys2, and avcc) should be connected to the 3.3-v dc supply. to oper- ate an interface at 5 v, the vccio pins associated with that i/o interface should be connected to 5 v. all supply pins of the same name should be connected to the same voltage plane. the different supply pins and their functions are described in this section. refer to the pin characteristics section beginning on page 24 of this data sheet for the internal vcc rail (vccio and vcc clamp) to which each pin is electri- cally attached. for more details about the information in this section, see the commercial and industrial operating voltage ranges beginning on page 80. also see table 51 on page 99 and its corresponding notes. typical power numbers on page 82 details the power consumption of each of these supply pins in maximum isa mode or internal lcd mode. vcc these supply pins are used to provide power to the lansc300 microcontroller core only. they should always be connected to a 3.3-v source. vcc1 this supply pin provides power to a subset of the lcd/alternate, power management, and isa inter- face pins. it can be connected to either a 3.3-v or 5-v source, depending on the logic threshold requirements of the external peripherals attached to these interfaces. when connected to the 5-v supply, all outputs with vcc1 as their vccio will be 5 v. if connected to 3.3 v, all of these outputs will be 3.3 v. vcc5 these supply pins are used to provide a 5-v source for the 5-v input and output pins. if the system design requires that the lansc300 microcontroller support 5-v tolerant inputs, then this pin should be con- nected to a 5-v dc source. this supply pin is the vccio for the parallel port, serial port, and pcmcia interfaces. vmem this supply pin controls the operating volt- age of the memory interface. when connected to the 5-v supply, all outputs to the main memory will be 5 v. this includes the lansc300 microcontroller data bus. therefore, translation buffers may be required when in- terfacing to 5-v devices on the data bus when the memory interface is operating at 3.3 v. vsys these supply pins provide power to a subset of the isa address and command signal pins, external memory chip selects, buffer direction controls, and other miscellaneous functions. they can be required to operate at 3.3 v or 5 v, depending on the system de- sign. vsys2 this supply pin controls the operating volt- age for some of the lcd/alternate function pins. this voltage pin should be connected to either 3.3 v or 5 v, depending on the type of bus option selected, the volt- age threshold requirements of attached devices, and the state of the other voltage pins associated with the lcd/alternate function interface pins (i.e., vcc1 and vsys). avcc this supply pin provides power to the analog section of the lansc300 microcontroller. it should al- ways be connected to a low-noise 3.3-v supply. for more information, see the dc characteristics specifica- tions, beginning on page 80. crystal specifications the lansc300 microcontroller on-chip oscillator is the primary clock source driving all of the on-chip pll clock generators and the real-time clock (rtc) function directly. for problems with crystal startup, check that the spec- ifications listed in this section are met, and refer to the troubleshooting guide for micro power off mode on lan tm sc300 and lansc310 microcontrollers and evaluation boards application note , order #21810. externally, a parallel resonant pc/at cut crystal (32.768 khz), two capacitors, and two resistors are re- quired for the oscillator to function properly. it is critical that the frequency of the oscillator circuit be as close as possible to the nominal 32.768 khz frequency for rtc accuracy. by selecting the appropriate external circuit components, this oscillator circuit can be made to op- erate at very close to the nominal 32.768 khz. figure 29 shows the complete oscillator circuit, includ- ing the discrete component model for the crystal. in this figure, the external discrete components that must be supplied by the system designer are r f , r b , c d , c g , and xtal. r f is the external feedback resistor for the on-chip amplifier. r b provides some isolation between the parasitic capacitance of the chip and the crystal. the value of this resistor also has a very small effect on the operating frequency of the circuit. c d and c g are the external load capacitors. the value of these capac- itors, in conjunction with the other capacitive values discussed below, have the most affect on the operating frequency of this circuit. the discrete components inside the dotted line repre- sent the circuit model for the crystal, with c o represent- ing the crystal lead shunt capacitance. the dashed line component c stray represents the stray capacitance of the printed circuit board. typically, a crystal manufac- turer provides values for all of the equivalent circuit 96 lan?sc300 microcontroller data sheet preliminary model components for a given crystal (i.e., l 1 , c 1 , r 1 , and c o ). in addition to these parameters, the manufac- turer will provide a load capacitance specification usu- ally designated as c l . the load capacitance specification is the capacitive load at which the manu- facturer has tuned the crystal for the specified fre- quency. it is therefore required that the load capacitance in the oscillator circuit is duplicated as closely as possible to the manufacturers load capaci- tance specification. the crystal load capacitance in the circuit consists of the capacitor network c o , c stray , c d , and c g . this net- work reduces to (c o + c stray ) in parallel with the series combination of c d and c g . therefore, the desired se- ries combination of c d and c g is equal to c l C (c o + c stray ), where c l is the crystal manufacturers load ca- pacitance specification. c stray is typically difficult to determine. some value can be assumed and experimentation will determine the optimal value for c d and c g . in determining the ex- ternal component values to provide the optimal operat- ing frequency, there are some recommended limits to ensure a reasonable start-up time for the oscillator cir- cuit. these limits are shown in table 49. table 49. recommended oscillator component value limits minimum maximum r f 14 m w 18 m w r b 0 w 10 k w c d 10 pf 30 pf c g 10 pf 30 pf the series combination of c d and c g = c ( d c g ) c d c g ) + ( -------------------------- - ? ? ? lansc300 microcontroller x32in (201) x32out (202) r f r b l 1 c 1 r 1 c o c d c g a b xtal c stray ab notes: for board layout suggestions, refer to the lansc300 microcontroller evaluation board users manual available in pdf for- mat on the amd web site. figure 29. x32 oscillator circuit lan?sc300 microcontroller data sheet 97 preliminary loop filters each of the phase-locked loops (plls) in the lansc300 microcontroller requires an external loop filter. figure 30 describes each of the loop filters and the recommended component values. the recom- mended component values are shown in table 50. the system designer shall include the pads on the printed circuit board to accommodate the future instal- lation/change of c2 and r1. this is recommended be- cause the pll performance can be affected by the physical circuit board design. in addition, future revi- sions of the lansc300 microcontroller with a modified pll design may require the addition of these compo- nents to the system board. the component value(s) of the loop filter directly af- fect the acquisition (start up) time of the pll circuit. with the values recommended, the approximate acqui- sition time is 200 ms. therefore, the system designer should program the clock control register at index 8fh appropriately. bits 0, 1, and 2 set the pll restart delay time. when the plls are shut off for any reason (i.e., power management), the pll will be allowed an amount of time equal to that programmed in this regis- ter to start up before the pll outputs are enabled for the internal device logic. a pll restart delay time of 256 ms should be set in the clock control register. the pulse width of the rstdrv signal is adjustable based on the pll start-up timing. see the timing spec- ifications in table 51 and figure 32Cfigure 35. table 10 on page 33 shows the pin characteristics for the loop filters, including the reset voltage level of each pin when resin is active. for more information about loop filters, see the trou- bleshooting guide for micro power off mode on the lan tm sc300 and elansc310 microcontrollers and evaluation boards application note, order #21810. notes: 1. when the pll is on, v lfx should be approximately be- tween 1 v and 2 v. table 50. loop-filter component values lfx r 1 c 1 c 2 100.47 m f not installed 200.47 m f not installed 300.47 m f not installed 400.47 m f not installed lfx r 1 c 1 c 2 figure 30. loop-filter component 98 lan?sc300 microcontroller data sheet preliminary ac switching characteristics and waveforms the ac specifications provided in the ac characteris- tics tables that follow consist of output delays, input setup requirements, and input hold requirements. fig- ure 31 provides a key to the switching waveforms. ac specifications measurement is defined by the fig- ures that follow each timing table. output delays are specified with minimum and maxi- mum limits, measured as shown. the minimum delay times are hold times provided to external circuitry. input setup and hold times are specified as minimums, defining the smallest acceptable sampling window. within the sampling window, a synchronous input sig- nal must be stable for correct microcontroller operation. figure 31. key to switching waveforms ac switching test waveforms notes: ac testing: inputs are driven at 3 v for a logic 1 and 0 v for a logic 0. waveforms inputs outputs must be steady will be steady may change from h to l will be changing from h to l may change from l to h will be changing from l to h dont care, any change permitted changing, state unknown does not apply center line is high-impedance off state vcc ? 2 vcc ? 2 v ih = vcc input v il = 0 test points output lan?sc300 microcontroller data sheet 99 preliminary ac switching characteristics over commercial and industrial operating ranges notes: 1. this parameter is dependent on the 32-khz oscillator start-up time. the oscillator start-up time is dependent on the external component values used, board layout, and power supply noise. see the crystal specifications section on page 95 for more information. 2. resin remains inactive during micro power off mode and micro power off mode exit. 3. the pulse width of rstdrv is adjustable based on pll startup timing. for more information, see loop filters on page 97. voltage sequencing on power-up for the lansc300 microcontroller should be observed as follows: Cvcc C all vcc clamp sources (vcc, vmem, vsys, vcc5, and avcc) C all vccio sources (vcc5, vmem, vsys, vcc1, vsys2, and avcc). the reverse is true when powering down. for any particular i/o pin, the vccio may come up simultaneously with the vcc clamp, but should never precede the vcc clamp. refer to the pin characteristics table (page 24) for detailed i/o information. table 51. power-up sequencing (see figures 32, 33, 34, and 35) symbol parameter description notes preliminary unit min typ max t1 all vcc valid to resin and ioreset inactive 1, 2 1 s t2 resin and ioreset inactive to rstdrv inactive 2, 3 300 m s t3 ioreset active to rstdrv active 0 ns t4 vsys2, vcc1, and vsys valid delay from vcc5 0 ns t5 vsys2, vcc1, vsys, and optionally vmem valid to ioreset inactive 5 m s t6 vcc5, vsys2, vcc1, vsys hold time from ioreset active 5 m s t7 vcc5 hold time from vsys2, vcc1, and vsys inactive 0 ns 100 lan?sc300 microcontroller data sheet preliminary figure 32. power-up sequence timing t 1 t 4 vcc/avcc vmem resin vcc5 vsys2 vcc1 vsys ioreset rstdrv t 2 note 1 notes: 1. rstdrv external driver is powered by: vccio = vsys and vcc clamp = vcc5. t 4 t 5 vcc/avcc vmem resin vcc5 vsys2 vcc1 vsys ioreset rstdrv notes: 1. rstdrv external driver is powered by: vccio = vsys and vcc clamp = vcc5. 2. the pulse width of rstdrv is adjustable based on pll startup timing. see the loop filters section on page 97 for more information. figure 33. micro power off mode exit note 1 note 2 lan?sc300 microcontroller data sheet 101 preliminary t 7 t 6 rstdrv vcc5 vsys2 vcc1 vsys vcc/avcc vmem resin notes: 1. rstdrv external driver is powered by: vccio = vsys and vcc clamp = vcc5. 2. a secondary power source could be applied at this time figure 34. entering micro power off mode (dram refresh disabled) ioreset t 3 note 1 note 2 2 dram refresh cycles t 7 ioreset vcc5 vsys2 vcc1 vsys vcc/avcc vmem resin notes: 1. rstdrv external driver is powered by: vccio = vsys and vcc clamp = vcc5. 2. a secondary power source could be applied at this time figure 35. entering micro power off mode (dram refresh enabled) note 2 rstdrv note 1 t 3 102 lan?sc300 microcontroller data sheet preliminary notes: these timings are based on 33-mhz operation (70 ns or faster dram recommended). table 52. dram memory interface, page hit and refresh cycle (see figures 36 and 37) symbol parameter description notes preliminary unit min max t30 ma valid setup to ras low 0 ns t31 ma hold from ras low 10 ns t32 ma setup to cas low 0 ns t37 cas precharge (page mode) 10 ns t38 ma hold from cas active 15 ns t39 ras to cas delay 20 ns t41 cas pulse width (page hit) 20 10,000 ns t42 mwe setup to cas low (page hit) 0 ns t43 mwe hold from cas low 15 ns t45 cas cycle time (page mode) 45 ns t46 cas low to d15Cd0 valid (read access time) 20 ns t47 d15Cd0 hold from cas high (read) 0 ns t48 d15Cd0 setup to cas low (write) 0 ns t49 d15Cd0 hold from cas low (write) 15 ns t50 cas low to ras low (refresh) 10 ns t51 cas hold from ras low (refresh) 70 ns t53 ras pulse width (suspend refresh) 80 ns lan?sc300 microcontroller data sheet 103 preliminary t43 t49 t30 t31 t39 t38 t32 t41 t46 t45 t47 t42 t48 ma10Cma0 ras cas mwe d15Cd0 figure 36. dram timings, page hit t37 t53 t50 t51 ras0 cas0 mwe figure 37. dram timings, refresh cycle 104 lan?sc300 microcontroller data sheet preliminary notes: for more information about dram first cycle read wait states, see the dram first cycle wait state select logic table in chapter 5 of the lan tm sc300 microcontroller programmers reference manual , order #18470. table 53. dram first cycle read access (see figure 38) symbol parameter description wait states min max unit t5a cas low to data valid (read access time) 120 ns 250 ns 380 ns t28a ras low to data valid (read access time) 150 ns 280 ns 3 110 ns t30 ma valid setup to ras low n/a 0 ns t31 ma hold from ras low n/a 10 ns t32 ma setup to cas low n/a 0 ns t33 ras hold from cas low n/a 20 ns t34 ras precharge from cas high n/a 10 ns t38 ma hold from cas active n/a 15 ns t39 ras to cas delay n/a 20 ns t40 ras pulse width n/a 70 10,000 ns t41a cas pulse width (read, first cycle) 130 ns 260 ns 390 ns t44a cas hold from ras low 160 ns 290 ns 3 120 ns table 54. dram bank/page miss read cycles (see figure 38) symbol parameter description wait state min max unit t5b cas low to data valid (read access time) 335 ns 465 ns 580 ns t28b ras low to data valid (read access time) 365 ns 495 ns 5 110 ns t29a cas precharge (page miss read) n/a 30 ns t33 ras hold from cas low n/a 20 ns t34 ras precharge from cas high n/a 10 ns t36 ras precharge (page miss) 338 ns 438 ns 553 ns t39 ras to cas delay n/a 30 ns t40 ras pulse width 70 10,000 ns lan?sc300 microcontroller data sheet 105 preliminary notes: for more information about dram bank miss read wait states, see the dram bank miss wait state select logic table in chapter 5 of the lan tm sc300 microcontroller programmers reference manual , order #18470. t41b cas pulse width (read, page miss) 345 ns 475 ns 590 ns t44b cas hold from ras low 375 ns 4 105 ns 5 120 ns t47 d15Cd0 hold from cas high (read) n/a 0 ns table 54. dram bank/page miss read cycles (see figure 38) (continued) symbol parameter description wait state min max unit t41a ras t36 t40 t38 t30 t31 t34 t44a t39 t5b t47 ma10Cma0 cas mwe d15Cd0 figure 38. dram first cycle and bank/page miss (read cycles) t32 first cycle bank/page miss t33 t5a t28a t28b t41b t39 t29a t44b 106 lan?sc300 microcontroller data sheet preliminary notes: for more information about dram first cycle write wait states, see the dram first cycle wait state select logic table in chapter 5 of the lan tm sc300 microcontroller programmers reference manual , order #18470. notes: for more information about dram bank miss wait states, see the dram bank miss wait state select logic table in chapter 5 of the lan tm sc300 microcontroller programmers reference manual , order #18470. table 55. dram first cycle write access (see figure 39) symbol parameter description wait state min max unit t5c d15Cd0 setup to cas low (write) n/a 5 ns t27d mwe setup to cas low (first cycle) n/a 20 ns t30 ma valid setup to ras low n/a 0 ns t31 ma hold from ras low n/a 10 ns t32 ma setup to cas low n/a 0 ns t33 ras hold from cas low n/a 20 ns t34 ras precharge from cas high n/a 10 ns t38 ma hold from cas active n/a 15 ns t39 ras to cas delay n/a 20 ns t40 ras pulse width n/a 70 10,000 ns t41d cas pulse width (first cycle, write) 115 ns 245 375 ns t43 mwe hold from cas low n/a 15 ns t44d cas hold from ras low (first cycle, write) 145 ns 275 ns 3 105 ns t49 d15Cd0 hold from cas low (write) n/a 15 ns table 56. dram bank/page miss write cycles (see figure 39) symbol parameter description wait state min max unit t5c d15Cd0 setup to cas low (write) n/a 5 ns t27c mwe to cas low 365 ns 465 ns 580 ns t29b cas precharge (page miss write) n/a 60 ns t33 ras hold from cas low n/a 20 ns t34 ras precharge from cas high n/a 10 ns t36 ras precharge 338 ns 438 ns 553 ns t39 ras to cas delay n/a 30 ns t40 ras pulse width n/a 70 10,000 ns t41c cas pulse width (page miss write) 330 ns 460 ns 575 ns t44c cas hold from ras low (page miss write) 360 ns 490 ns 5 105 ns t49 d15Cd0 hold from cas low (write) n/a 15 ns lan?sc300 microcontroller data sheet 107 preliminary t41d ras t36 t40 t38 t30 t31 t34 t44d t39 t27d t43 t5c t49 t5c ma10Cma0 cas mwe d15Cd0 figure 39. dram first cycle and bank/page miss (write cycles) t33 t32 first cycle bank/page miss t49 t29b t41c t27c t39 t44c 108 lan?sc300 microcontroller data sheet preliminary table 57. local bus interface (see figure 40) symbol parameter description notes preliminary unit min max t1 cpuclk period 14 ns t2 cpuclk pulse width low 7 ns t3 cpuclk pulse width high 7 ns t4 ads delay from cpuclk 3 15 ns t5 a[23C1] ble , bhe , w/r ,d/c , m/io delay from cpuclk 5 23 ns t6a ldev valid from address or control (non-zero wait state) 2 20 ns t6b ldev valid from address or control (zero wait state) 2 18 ns t7 lrdy valid from cpuclk 2 12 ns t8 lrdy high impedance from cpuclk 0 5 ns t9 cpurdy delay from cpuclk 5 26 ns t10 cpurdy high impedance from cpuclk 0 5 ns t11 d15Cd0 setup to cpuclk (read) 7 ns t12 d15Cd0 hold from cpuclk (read) 0 0 ns t13 d15Cd0 valid from cpuclk (write) 5 20 ns lan?sc300 microcontroller data sheet 109 preliminary figure 40. local bus interface t1 t1 t2 t3 t11 t4 t5 t6a t6b t6a t7 t8 t8 t9 t9 t10 t12 t13 t13 cpuclk ads a23Ca12 ldev lrdy cpurdy d15Cd0 (in) d15Cd0 (out) 110 lan?sc300 microcontroller data sheet preliminary notes: 1. these timings are always controlled via refresh cycle generation and are therefore based on the programmed refresh rate for the system. lvee active always follows lvdd active by one refresh cycle. this sequence will always occur when the system exits reset or when the system transitions from the suspend mode to high-speed pll mode. the default refresh rate after reset is 15.0 m s. see the lan tm sc300 microcontroller programmers reference manual , order #18470, for a full description of the power management unit and the refresh control mechanisms. 2. lvee will always be forced to inactive whenever the device enters the sleep mode, or whenever the video pll is forced off in doze mode. lvee will remain inactive in suspend mode. lvdd will remain active until the device enters the suspend mode, at which point it will be forced inactive. 3. the lcd panel data and control signals are all forced to a logical 0 in the power management modes that are programmed to disable the video pll (i.e., the video pll may be disabled in doze, sleep, and suspend modes). these signals will be re- driven whenever lvdd is driven active. table 58. video ram/lcd interface (see figures 41 and 42) symbol parameter description notes preliminary unit min max t81 dsmd hold from dsma change 5 ns t82 display ram read cycle pulse width 85 ns t83 dsmd active from dswe active 50 ns t84 dsmd setup to dswe inactive 15 ns t85 dsma hold from dswe inactive 5 ns t86 dsmd hold from dswe inactive 0 ns t87 display ram write cycle pulse width 65 ns t88 dsmd tri-state delay from dsoe high 5 30 ns t89 dsmd delay from dsoe active 5 30 ns t90 panel data setup to cp2 (data clock) 5 ns t91 panel data hold from cp2 (data clock) 10 ns t92 panel data delay from cp2 (data clock) 10 ns t93 cp2 allowance time from cp1 (latch pulse) 65 ns t94 cp1 allowance time from cp2 65 ns t95 frm setup time 520 ns t96 frm hold time 520 ns t97 dsma setup to dswe active 0 ns table 59. power management control signals (not shown) no. parameter description notes preliminary units min max extsmi pulse width 10 ns sus /res pulse width 100 ns lvdd active low to lvee active low 1, 3 lvee inactive to lvdd inactive 2, 3 lan?sc300 microcontroller data sheet 111 preliminary dsmd7Cdsmd0 dsma14Cdsma0 t87 t82 t84 t85 t97 t81 t88 t83 t86 t89 dscs dsoe dswe figure 41. display sram timings lcdd3C lcdd0 t93 t94 t96 t92 t90 t91 t95 cp1 cp2 frm figure 42. lcd interface timings 112 lan?sc300 microcontroller data sheet preliminary notes: 1. violates for 600 ns (3.3 v) pcmcia read cycle only. 2. pcmcia specifies 35 ns for a 600 ns cycle, 20 ns for 250 and 200 ns cycles, and 15 ns for a 100 ns cycle. 3. if pcmcia is buffered, this hold time may be increased by propagation delay through the buffer. 4. if the pcmcia address buffer is controlled via the mce signals, the output disable/enable delay of the buffer will affect the address setup and hold from memr . 5. wait_ab asserted for longer that 10 m s may cause a dram ras low (max) to be violated if the extended pcmcia cycle occurs during a dram page hit. (see the t rasc max parameter for a particular dram.) the ras active timer (10 m s) will not force ras inactive while the extended pcmcia cycle is occurring. these timings are based on default device settings and required initial programming. these timings may be modified via the mms memory wait state 1 and 2 registers, index 62h and index 50h, and the command delay register, index 60h. (see the lan tm sc300 microcontroller programmers reference manual , order #18470.) table 60. pcmcia memory read cycle (see figure 43) symbol parameter description notes preliminary unit min max t1a data setup before memr inactive (8 bit) 40 ns t1b data setup before memr inactive (16 bit) 25 ns t2 data hold following memr 0ns t3 memr width time 550 ns t4a address setup before memr (8 bit) 1 155 ns t4b address setup before memr (16 bit) 60 ns t5 address hold following memr 2, 3 0 ns t6a mce setup before memr (8 bit) 4 175 ns t6b mce setup before memr (16 bit) 4 45 ns t7 mce hold after memr 2, 4 0 ns t8 memr inactive from wait_ab inactive 120 ns t9 wait_ab delay falling from memr 35 ns t10 wait_ab pulse width time 5 12,000 ns t11 icdir setup before memr C1 ns t12 icdir hold after memr 0ns t13 dbufoe setup before memr C2 ns t14 dbufoe hold after memr C2 ns t15a endirh, endirl setup before memr (8 bit) 170 ns t15b endirh, endirl setup before memr (16 bit) 45 ns t16 endirh, endirl hold from memr C4 ns lan?sc300 microcontroller data sheet 113 preliminary sa25Csa0 wait_ab d15Cd0 memr reg /mce t3 t4a t4b t5 t6a t6b t7 t1a t1b t2 t9 t10 t8 t11 t12 t13 t14 t15a t15b t16 icdir dbufoe endirh, endirl figure 43. pcmcia memory read cycle 114 lan?sc300 microcontroller data sheet preliminary notes: 1. wait_ab asserted for longer that 10 m s may cause a dram ras low (max) to be violated if this extended pcmcia cycle occurs during a dram page hit. (see the t rasc max parameter for a particular dram.) the ras active timer (10 m s) will not force ras inactive while the extended pcmcia cycle is occurring. these timings are based on default device settings and required initial programming. these timings may be modified via the mms memory wait state registers 1 and 2, index 62h and index 50h, and command delay register, index 60h. (see the lan tm sc300 microcontroller programmers reference manual, order #18470.) table 61. pcmcia memory write cycle (see figure 44) symbol parameter description notes preliminary units min max t2 data hold following memw 50 ns t3 memw width time 500 ns t4a address setup before memw (8 bit) 150 ns t4b address setup before memw (16 bit) 60 ns t5 address hold following memw 50 ns t6a mce setup before memw (8 bit) 175 ns t6b mce setup before memw (16 bit) 45 ns t7 mce hold after memw 40 ns t8a output enable (memr ) setup before memw (8 bit) 200 ns t8b output enable (memr ) setup before memw (16 bit) 100 ns t9a output enable (memr ) hold after memw (8 bit) 250 ns t9b output enable (memr ) hold after memw (16 bit) 150 ns t10 memw inactive from wait_ab inactive 100 ns t11 wait_ab delay falling from memw 35 ns t12 wait_ab pulse width time 1 12,000 ns t13a dbufoe setup before memw (8 bit) 150 ns t13b dbufoe setup before memw (16 bit) 50 ns t14 dbufoe hold after memw 50 ns lan?sc300 microcontroller data sheet 115 preliminary t4a t4b t3 t5 t6a t6b t7 t2 t11 t12 t10 t13a t13b t14 t8a t8b t9a t9b sa25Csa0 reg /mce memw wait_ab d15Cd0 dbufoe memr figure 44. pcmcia memory write cycle 116 lan?sc300 microcontroller data sheet preliminary notes: 1. pcmcia specifies 20 ns (min) for 5 v i/o cards. 2. if the pcmcia address buffer is controlled via the mce signals, the output disable/enable delay of the buffer will affect the address setup and hold from memr . 3. wait_ab asserted for greater that 10 m s may cause a dram ras low (max) to be violated if the extended pcmcia cycle occurs during a dram page hit. (see the t rasc max parameter for a particular dram.) the ras active timer (10 m s) will not force ras inactive while the extended pcmcia cycle is occurring. these timings are based on default device settings and required initial programming. these timings may be modified via the wait state control and command delay register. (see the lan tm sc300 microcontroller programmers reference manual , order #18470.) table 62. pcmcia i/o read cycle (see figure 45) symbol parameter description notes version b3 preliminary version b4 preliminary units min max min max t1 data setup before ior 40 40 ns t2 data hold following ior 00ns t3a ior width time (8 bit) 560 490 ns t3b ior width time (16 bit) 280 225 ns t4a address setup before ior (8 bit) 150 150 ns t4b address setup before ior (16 bit) 115 115 ns t5 address hold following ior 1C1 50 ns t6a mcel setup before ior (8 bit) 2 160 160 ns t6b mcel setup before ior (16 bit) 100 100 ns t7 mce hold after ior 1, 2 5 65 ns t8 reg setup before ior 55ns t9 reg hold after ior 065ns t10 iois16 delay falling from address 35 35 ns t11 iois16 delay rising from address 35 35 ns t12 wait_ab delay falling from ior 35 35 ns t13 wait_ab pulse width time 3 12,000 12,000 ns t14 icdir setup before ior C5 C5 ns t15 icdir hold after ior 05ns t16 dbufoe setup before ior C3 C3 ns t17 dbufoe hold after ior C3 45 ns t18a endirh, endirl setup before ior (8 bit) 170 170 ns t18b endirh, endirl setup before ior (16 bit) 110 110 ns t19 endirh, endirl hold from ior C6 45 ns t20 mceh delay from iois16 active 50 50 ns t21 ior inactive from wait_ab inactive 100 100 ns lan?sc300 microcontroller data sheet 117 preliminary mceh t3a t3b sa15Csa0 t11 t4a t4b t5 t8 t9 t6a t6b t7 t1 t2 t10 t12 t13 t14 t15 t16 t17 t18a t18b t19 reg mcel ior iois16 wait_ab d15Cd0 icdir dbufoe endirh, endirl figure 45. pcmcia i/o read cycle t21 t20 118 lan?sc300 microcontroller data sheet preliminary notes: 1. wait_ab asserted for longer than 10 m s may cause a dram ras low (max) to be violated if this extended pcmcia cycle occurs during a dram page hit. (see the t rasc max parameter for a particular dram.) the ras active timer (10 m s) will not force ras inactive while the "extended" pcmcia cycle is occurring. 2. pcmcia specifies 60 ns minimum for data setup to i/o write active. these timings are based on default device settings and required initial programming. these timings may be modified via the wait state control and command delay registers. (see the lan tm sc300 microcontroller programmers reference manual, order #18470.) table 63. pcmcia i/o write cycle (see figure 46) symbol parameter description notes preliminary units min max t1 data setup before iow active 2 25 ns t2 data hold following iow 50 ns t3a iow width time (8 bit) 440 ns t3b iow width time (16 bit) 165 ns t4a address setup before iow (8 bit) 175 ns t4b address setup before iow (16 bit) 165 ns t5 address hold following iow 50 ns t6a mcel setup before iow (8 bit) 215 ns t6b mcel setup before iow (16 bit) 160 ns t7 mce hold after iow 50 ns t8a reg setup before iow (8 bit) 230 ns t8b reg setup before iow (16 bit) 170 ns t9 reg hold after iow 50 ns t10 iois16 delay falling from address 35 ns t11 iois16 delay rising from address 35 ns t12 wait_ab delay falling from iow 35 ns t13 wait_ab pulse width time 1 12,000 ns t14a dbufoe setup before iow (8 bit) 230 ns t14b dbufoe setup before iow (16 bit) 165 ns t15 dbufoe hold after iow 50 ns t16 mceh delay from iois16 active 50 ns t17 iow inactive from wait_ab inactive 100 ns lan?sc300 microcontroller data sheet 119 preliminary t13 t4a t4b t5 t11 t8a t8b t9 t6a t6b t7 t1 t2 t10 t12 t14a t14b t15 sa25Csa0 reg mcel mceh iow iois16 wait_ab d15Cd0 dbufoe figure 46. pcmcia i/o write cycle t16 t17 t3a t3b 120 lan?sc300 microcontroller data sheet preliminary notes: 1. this is the timing when romcs is qualified with memr or memw , (bit 2 of the miscellaneous 5 register, index b3h, = 0.) 2. this is the timing when romcs is configured as an address decode, (bit 2 of the miscellaneous 5 register, index b3h, = 1.) these timings are based on default wait state settings, set for three wait states in bits 4 and 7 of the command delay register, index 60h, and required initial programming. these timings may be modified via the mms memory wait state 1 register, index 62h, and the command delay register, index 60h. (see the lan tm sc300 microcontroller programmers reference manual , order #18470.) for fast romcs (bios rom) accesses, set bit 6 of miscellaneous 5 register, index b3h. bits 4 and 5 control wait states when fast romcs is enabled. for more information, see table 66, dos rom and fast dos rom read/write 16- bit cycles (see figure 49), on page 124. also see the lan tm sc300 and lan tm sc310 devices isa bus anomalies application note , order #20747. table 64. bios rom read/write 8-bit cycle (see figure 47) symbol parameter description notes preliminary units min max t1a sa stable to romcs active 1 55 ns t1b sa stable to romcs active 2 5 ns t2a sa hold from romcs inactive (write) 1 50 ns t2b sa hold from romcs inactive (read) 1 0 ns t3a romcs pulse width (read) 1 390 ns t3b romcs pulse width (write) 1 335 ns t4a memw active to romcs active 1 2 ns t4b memr active to romcs active 1 1 ns t5a romcs hold from memw inactive 1 0 ns t5b romcs hold from memr inactive 1 0 ns t6 rddata setup to command inactive 40 ns t7 rddata hold from command inactive 0 ns t8 wrdata setup to command inactive 200 ns t9 wrdata hold from command inactive 50 ns t10 dbufoe active from command 5 ns t11a dbufoe hold from memw 50 ns t11b dbufoe hold from memr C2 ns t12 endirh, endirl setup before memr 50 ns t13 endirh, endirl hold from memr C4 ns t14 romcs active to command active 2 65 ns t15 romcs hold from sa 2 5 ns lan?sc300 microcontroller data sheet 121 preliminary t1b t2a t2b t4a t4b t5a t5b t6 t7 t9 t10 t11a t11b t12 t13 0 = read sa23Csa0 romcs memr /w rddata wrdata dbufoe endirh, endirl t1a t3a t3b t8 figure 47. bios rom read/write 8-bit cycle t14 t15 122 lan?sc300 microcontroller data sheet preliminary notes: 1. this is the timing when doscs is qualified with memr or memw, (bit 4 of rom configuration 3 register, index b8h, = 0). 2. this is the timing when doscs is configured as an address decode, (bit 4 of rom configuration 3 register, index b8h, = 1). these timings are based on default settings with bit 2 in index 50h set to 0 and bits 0 and 1 in index 62h equal to 0 for 5 wait states, and required initial programming. these timings may be modified via the mms memory wait state 1 register, index 62h, the command delay register, index 60h, and the mms memory wait state 2 register index 50h. (see the lan tm sc300 micro- controller programmers reference manual , order #18470.) table 65. dos rom read/write 8-bit cycle (see figure 48) symbol parameter description notes preliminary units min max t1a sa stable to doscs active 1 160 ns t1b sa stable to doscs active 2 5 ns t2a sa hold from doscs inactive (write) 1 50 ns t2b sa hold from doscs inactive (read) 1 0 ns t3a doscs pulse width (read) 1 550 ns t3b doscs pulse width (write) 1 500 ns t4a memw active to doscs active 1 4 ns t4b memr active to doscs active 1 4 ns t5a doscs hold from memw inactive 1 0 ns t5b doscs hold from memr inactive 1 0 ns t6 rddata setup to command inactive 40 ns t7 rddata hold from command inactive 0 ns t8 wrdata setup to command inactive 90 ns t9 wrdata hold from command inactive 50 ns t10 dbufoe active from command 5 ns t11a dbufoe hold from memw 50 ns t11b dbufoe hold from memr C2 ns t12 endirh, endirl setup to memr 50 ns t13 endirh, endirl hold from memr C3 ns t14 doscs active to command active 2 170 ns t15 doscs hold from sa 2 5 ns lan?sc300 microcontroller data sheet 123 preliminary t15 t7 t1a t3a t3b t6 t8 t9 t10 t12 t13 0 = read sa19Csa0 doscs memr /w rddata wrdata dbufoe endirh, endirl figure 48. dos rom read/write 8-bit cycle t2a t2b t4a t4b t5a t5b t11a t11b t1b t14 124 lan?sc300 microcontroller data sheet preliminary notes: 1. this is the timing when doscs is qualified with memr or memw, (bit 4 of rom configuration 3 register, index b8h, = 0). 2. this is the timing when doscs is configured as an address decode, (bit 4 of rom configuration 3 register, index b8h, = 1). these timings are based on index 51h, bit 1 set for 16-bit doscs cycles, and required initial programming. the standard dos rom timings are based on the default wait state settings in bits 2 and 3 of the mms memory wait state register, index 62h, set to 4 wait states. the fast dos rom timings are based on index b8h, bit 7 set for doscs cycles to run at high-speed with the default setting in bits 5 and 6 for 4-wait states. these timings may be modified via the command delay register, index 60h. (see the lan tm sc310 microcontroller program- mers reference manual , order #18470.) for more information about fast dos rom cycles, see the lan tm sc300 and lan tm sc310 devices isa bus anomalies appli- cation note , order #20747. the fast dos rom timings shown here also apply to fast bios rom (romcs) accesses controlled by miscellaneous 5 register, index b3h. table 66. dos rom and fast dos rom read/write 16-bit cycles (see figure 49) symbol parameter description notes standard dos rom preliminary fast dos 33 mhz preliminary fast dos 25 mhz preliminary units min max min max min max t1a sa stable to doscs active 1 65 25 25 ns t1b sa stable to doscs active 2 5 5 8 ns t2a sa hold from doscs inactive (write) 1 50 15 20 ns t2b sa hold from doscs inactive (read) 1 0 0 0 ns t3a doscs pulse width (read) 1 550 130 250 ns t3b doscs pulse width(write) 1 500 100 175 ns t4a memw active to doscs active 1 3 3 3 ns t4b memr active to doscs active 1 4 4 4 ns t5a doscs hold from memw inactive 1 0 0 0 ns t5b doscs hold from memr inactive 1 0 0 0 ns t6 rddata setup to command inactive 25 25 33 ns t7 rddata hold from command inactive 0 0 0 ns t8 wrdata setup to command inactive 400 120 160 ns t9 wrdata hold from command inactive 45 15 20 ns t10 dbufoe active from command 5 5 0 ns t11a dbufoe hold from memw 50 15 20 ns t11b dbufoe hold from memr C2 C2 0 ns t12 endirh, endirl setup to memr 50 15 20 ns t13 endirh, endirl hold from memr C4 C4 C4 ns t14 doscs active to command active 2 65 15 20 ns t15 doscs hold from sa 25 5 5 ns t16a memr pulse width 550 130 250 ns t16b memw pulse width 500 100 175 ns lan?sc300 microcontroller data sheet 125 preliminary t1a t3a t3b t6 t8 t7 t9 t10 t12 t13 0 = read sa23Csa0 doscs memr /w rddata wrdata dbufoe endirh, endirl figure 49. dos rom read/write 16-bit cycle t2a t2b t4a t4b t5a t5b t11a t11b t1b t15 t14 t16a,b 126 lan?sc300 microcontroller data sheet preliminary : notes: these timings are based on default settings and required initial programming. these timings may be modified via the mms memory wait state1 register, index 62h, and the command delay register, index 60h. (see the lan tm sc300 microcontroller programmers reference manual , order #18470.) table 67. isa memory read/write 8-bit cycle (see figure 50) symbol parameter description notes preliminary units min max t1 la stable to bale inactive 60 ns t2 sa stable to command active 160 ns t3 bale pulse width 35 ns t4 la hold from bale inactive 40 ns t5a sa hold from command inactive write 50 ns t5b sa hold from command inactive read 0 ns t6 bale inactive to command active 140 ns t7a memw command pulse width 500 ns t7b memr command pulse width 550 ns t8a memw active to iochrdy inactive 340 ns t8b memr active to iochrdy inactive 340 ns t9a memw hold from iochrdy active 110 ns t9b memr hold from iochrdy active 160 ns t10 rddata setup to command inactive 40 ns t11 rddata hold from command inactive 0 ns t12 wrdata setup to command inactive 300 ns t13 wrdata hold from command inactive 50 ns t14 dbufoe active from command 5 ns t15a dbufoe hold from memw 50 ns t15b dbufoe hold from memr C2 ns t16 endirh, endirl setup to memr 170 ns t17 endirh, endirl hold from memr C4 ns t18 la stable to sa stable 15 ns t19 sa stable to bale inactive 45 ns lan?sc300 microcontroller data sheet 127 preliminary t6 t1 t3 t4 t2 t10 t12 t11 t13 t14 t16 t17 0 = read bale la23Cla17 sa23Csa0 memr /w iochrdy rddata wrdata dbufoe endirh, endirl figure 50. isa memory read/write 8-bit cycle t5a t5b t15a t15b t7a t7b t8a t8b t9a t9b t18 t19 128 lan?sc300 microcontroller data sheet preliminary notes: these timings are based on default settings and required initial programming. these timings may be modified via the mms memory wait state 1 register, index 62h, and the command delay register, index 60h. (see the lan tm sc300 microcontroller programmers reference manual , order #18470.) table 68. isa memory read/write 16-bit cycle (see figure 51) symbol parameter description notes preliminary units min max t1 la stable to bale inactive 60 ns t2 sa stable to command active 70 ns t3 bale pulse width 35 ns t4 la hold from bale inactive 40 ns t5a sa hold from command inactive write 50 ns t5b sa hold from command inactive read 0 ns t6 bale inactive to command active 30 ns t7a la stable to mcs16 valid 35 ns t7b mcs16 hold from la change 0 ns t8a memw command pulse width 500 ns t8b memr command pulse width 550 ns t9a memw active to iochrdy inactive 340 ns t9b memr active to iochrdy inactive 340 ns t10a memw hold from iochrdy active 110 ns t10b memr hold from iochrdy active 160 ns t11 rddata setup to command inactive 25 ns t12 rddata hold from command inactive 0 ns t13 wrdata setup to command inactive 330 ns t14 wrdata hold from command inactive 50 ns t15 dbufoe active from command 5 ns t16a dbufoe hold from command write 50 ns t16b dbufoe hold from command read C2 ns t17 endirh, endirl setup to memr 50 ns t18 endirh, endirl hold from memr C4 ns t19 sa (23:13) stable to mcs16 valid 25 ns t20 la stable to sa stable 15 ns t21 sa stable to bale inactive 45 ns lan?sc300 microcontroller data sheet 129 preliminary t2 t1 t3 t4 t6 t11 t13 t7b t12 t14 t15 t17 t18 0 = read bale la23Cla17 sa23Csa0 memr /w mcs16 iochrdy rddata wrdata dbufoe endirh, endirl figure 51. isa memory read/write 16-bit cycle t5a t5b t10a t10b t7a t8a t8b t9a t9b t16a t16b t20 t21 130 lan?sc300 microcontroller data sheet preliminary notes: 1. if the data bus is externally buffered and/or level translated, this write data hold time will be increased by the propagation delay through the buffer and/or the output disable delay of the buffer. these timings are based on default settings and required initial programming. these timings may be modified via the mms memory wait state 1 register, index 62h, and the command delay register, index 60h. (see the lan tm sc300 microcontroller programmers reference manual , order #18470.) table 69. isa memory read/write 0 wait state cycle (see figure 52) symbol parameter description notes preliminary units min max t1 la stable to bale inactive 60 ns t2 sa stable to command active 70 ns t3 bale pulse width 35 ns t4 la hold from bale inactive 40 ns t5a sa hold from command inactive write 0 ns t5b sa hold from command inactive read 0 ns t6 bale inactive to command active 30 ns t7 la stable to mcs16 active 35 ns t8 command pulse width 100 ns t9 command active to 0ws active 0 20 ns t10 0ws hold from command inactive 40 ns t11 mcs16 hold from la change 0 ns t12 rddata setup to command inactive 25 ns t13 rddata hold from command inactive 0 ns t14 wrdata setup to command inactive 100 ns t15 wrdata hold from command inactive 1 C1 ns lan?sc300 microcontroller data sheet 131 preliminary t1 t3 t4 t2 t8 t12 t14 t7 t11 t9 t10 t13 t15 bale la23Cla17 sa23Csa0 memr /w mcs16 0ws rddata wrdata figure 52. isa memory read/write 0 wait state cycle t6 t5a t5b 132 lan?sc300 microcontroller data sheet preliminary notes: 1. these timings apply only to the b4 version of the lansc300 microcontroller. the timings for the b3 version are t2b = 0 ns, t3b = 550 ns, t11b = -2 ns, and t13 = -4 ns. these timings may be modified via the mms memory wait state 1 register, index 62h, and the command delay register, index 60h. (see the lan tm sc300 microcontroller programmers reference manual , order #18470.) table 70. isa i/o 8-bit read/write cycle (see figure 53) symbol parameter description notes preliminary units min max t1a sa stable to iow active 200 ns t1b sa stable to ior active 150 ns t2a sa hold from iow inactive 50 ns t2b sa hold from ior inactive 1 50 ns t3a iow pulse width 450 ns t3b ior pulse width 1 505 ns t4a iow active to iochrdy inactive 300 ns t4b ior active to iochrdy inactive 350 ns t5a iow hold from iochrdy active 110 ns t5b ior hold from iochrdy active 160 ns t6 rddata setup to command inactive 40 ns t7 rddata hold from command inactive 0 ns t8 wrdata setup to command inactive 400 ns t9 wrdata hold from command inactive 50 ns t10 dbufoe active from command 5 ns t11a dbufoe hold from command write 50 ns t11b dbufoe hold from command read 1 50 ns t12 endirh, endirl setup to ior 150 ns t13 endirh, endirl hold from ior 150 ns t14 bale pulse width 50 ns lan?sc300 microcontroller data sheet 133 preliminary t6 t8 t7 t9 t10 t12 t13 0 = read sa15Csa 0 ior /w iochrdy rddata wrdata dbufoe endirh, endirl t2a t2b t11a t11b t1a t1b t5a t5b t3a t3b t4a t4b figure 53. isa i/o 8-bit read/write cycle t14 bale 134 lan?sc300 microcontroller data sheet preliminary notes: 1. these timings apply to the b4 version of the lansc300 microcontroller only. the timings for the b3 version are t5b = 260, t6b = 0, t12b = -2 ns, and t14 = -4 ns. these timings are based on default settings and required initial programming. these timings may be modified via the mms memory wait state1 register, index 62h, and the command delay register, index 60h. (see the lan tm sc300 microcontroller programmers reference manual, order #18470.) table 71. isa i/o 16-bit read/write cycle (see figure 54) symbol parameter description notes preliminary units min max t1a sa stable to iow active 200 ns t1b sa stable to ior active 150 ns t2 sa stable to iocs16 active 95 ns t3a iow active to iochrdy inactive 30 ns t3b ior active to iochrdy inactive 80 ns t4a iow hold from iochrdy active 110 ns t4b ior hold from iochrdy active 160 ns t5a iow pulse width 160 ns t5b ior pulse width 1 225 ns t6a sa hold from iow inactive 50 ns t6b sa hold from ior inactive 1 50 ns t7 rddata setup to command inactive 40 ns t8 rddata hold from command inactive 0 ns t9 wrdata setup to command inactive 250 ns t10 wrdata hold from command inactive 50 ns t11 dbufoe active from command 5 ns t12a dbufoe hold from command write 50 ns t12b dbufoe hold from command read 1 50 ns t13 endrih, endirl setup to ior 100 ns t14 endirh, endirl hold from ior 150 ns t15 bale pulse width 50 ns lan?sc300 microcontroller data sheet 135 preliminary t13 t5a t5b t7 t9 t2 t8 t10 t11 t14 0 = read sa15Csa0 ior /w iocs16 iochrdy rddata wrdata dbufoe endirh, endirl figure 54. isa i/o 16-bit read/write cycle t12a t12b t1a t1b t3a t3b t4a t4b t6a t6b t15 bale 136 lan?sc300 microcontroller data sheet preliminary notes: the appropriate timings above are valid for the bidirectional parallel port mode also. timings t13 and t14 are also valid for the unidirectional parallel port mode. ( ppdcs is ppwde in unidirectional mode.) table 72. epp data register write cycle (see figure 55) symbol parameter description max min unit t0 afdt delay from iow active 8.4 4.9 ns t1 afdt delay from ppdcs active 1.8 1.1 ns t2 afdt delay from ppoen active 1.0 0.8 ns t3 afdt active pulse width (no wait states added) 450 448 ns t4 afdt high to low recovery 1000 ns t5 afdt low to strb low C0.2 ns t6 strb delay from ppdcs active 1.6 0.9 ns t7 strb delay from ppoen active 0.8 0.6 ns t8 afdt high to strb high delay C2.4 C1.4 ns t9 strb low to data valid delay 3.7 ns t10 strb high to data valid hold 4.0 ns t11 ppoen delay from iow active 7.4 ns t12 ppoen delay from iow inactive 1.1 ns t13 ppdcs delay from iow active 6.6 ns t14 ppdcs delay from iow inactive 4.3 ns t15 afdt hold from busy high 139 129 ns t16 busy low delay from afdt active 307 ns t3 t1 t2 t0 t15 t4 t5 t7 t8 t9 t10 t16 t11 t12 t13 t14 valid data afdt strb d7Cd0 busy ppoen ppdcs iow ior t6 figure 55. epp data register write cycle lan?sc300 microcontroller data sheet 137 preliminary notes: the appropriate timings above are also valid for the bidirectional parallel port mode. table 73. epp data register read cycle (see figure 56) symbol parameter description max min unit t1 afdt delay from ppdcs active 1.8 1.1 ns t2 afdt active pulse width (no wait states) 450 448 ns t3 afdt high to low recovery 1000 ns t4 read data valid delay 25.3 ns t5 read data hold time 2.3 ns t6 ppdcs delay from ior active 6.8 ns t7 ppdcs delay from afdt inactive 3.7 1.8 ns t8 ppdcs delay from ior inactive 4.2 ns t9 busy (inactive) hold from afdt high 0 ns t1 t2 t3 t4 t5 t6 t8 t7 t9 data valid afdt strb d7Cd0 ppdcs ppoen ior iow busy figure 56. epp data register read cycle 138 lan?sc300 microcontroller data sheet preliminary 25.50 ref 27.90 28.10 30.40 30.80 25.50 ref 27.90 28.10 30.40 30.80 pin 208 pin 104 pin 52 0.25 min 3.20 3.60 0.50 basic 16-038-pqr-1_ah pqr208 ec95 8-13-97 lv pin 156 3.95 max seating plane pin 1 i.d. physical dimensions pqr 208, trimmed and formed plastic shrink quad flat pack (qfp) notes: 1. all measurements are in millimeters unless otherwise noted. 2. not to scale. for reference only. lan?sc300 microcontroller data sheet 139 preliminary 29.80 30.20 27.80 28.20 29.80 30.20 27.80 28.20 1 208 1.00 ref. 1.60 max 11 ?13 11 ?13 0.50 bsc 1.35 1.45 16-038-pqt-1_al pql208 9.4.97 lv 52 physical dimensions (continued) pql 208, trimmed and formed thin quad flat pack (tqfp) notes: 1. all measurements are in millimeters unless otherwise noted. 2. not to scale. for reference only. trademarks amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am386 and am486 are registered trademarks of advanced micro devices, inc. e86, k86, and lan are trademarks of advanced micro devices, inc. fusione86 is a service mark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies. |
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